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path: root/src/arch/arm/isa/operands.isa
AgeCommit message (Expand)Author
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-01-18O3: Fix itstate prediction and recovery.Matt Horsnell
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black
2010-06-02ARM: Decode to specialized conditional/unconditional versions of instructions.Gabe Black
2010-06-02ARM: Implement the bkpt instruction.Gabe Black
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02ARM: Make integer division by zero return a fault.Gabe Black
2010-06-02ARM: Add some support for wfi/wfe/yield/etcAli Saidi
2010-06-02ARM: Add fp operands to operands.isa.Gabe Black
2010-06-02ARM: Allow flattening into any mode.Gabe Black
2010-06-02ARM: Implement the strex instructions.Gabe Black
2010-06-02ARM: Squash the low order bits of the PC when performing a regular branch.Gabe Black
2010-06-02ARM: When changing the CPSR and branching, make sure the branch is second.Gabe Black
2010-06-02ARM: Explicitly keep track of the second destination for double loads/stores.Gabe Black
2010-06-02ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.Gabe Black
2010-06-02ARM: Add a base class to support usada8.Gabe Black
2010-06-02ARM: Make LDM that loads the PC perform an interworking branch.Gabe Black
2010-06-02ARM: Align the PC when using it as the base for a load.Gabe Black
2010-06-02ARM: Add support for interworking branch ALU instructions.Gabe Black
2010-06-02ARM: Add an fp version of one of the microop indexed registers.Gabe Black
2010-06-02ARM: Eliminate the unused rhi and rlo operands.Gabe Black
2010-06-02ARM: Implement all integer multiply instructions.Gabe Black
2010-06-02ARM: Implement branch instructions external to the decoder.Gabe Black
2010-06-02ARM: Replace the interworking branch base class with a special operand.Gabe Black
2010-06-02ARM: Fix PC operand handling.Gabe Black
2010-06-02ARM: Add new base classes for data processing instructions.Gabe Black
2010-06-02ARM: Define the load instructions from outside the decoder.Gabe Black
2010-06-02ARM: Add an operand for accessing the current PC.Gabe Black
2010-06-02ARM: Track the current ISA mode using the PC.Gabe Black