| Age | Commit message (Expand) | Author |
|---|
| 2018-02-07 | arch-arm: Change function name for banked miscregs | Giacomo Travaglini |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-07-13 | arch-arm: fix ldm of pc interswitching branch | Gedare Bloom |
| 2017-07-05 | arch: ISA parser additions of vector registers | Rekai Gonzalez-Alberquilla |
| 2016-06-02 | arm: Rewrite ERET to behave according to the ARMv8 ARM | Andreas Sandberg |
| 2014-04-29 | arm: use condition code registers for ARM ISA | Curtis Dunham |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2012-09-25 | ARM: Inst writing to cntrlReg registers not set as control inst | Nathanael Premillieu |
| 2011-07-05 | ISA parser: Define operand types with a ctype directly. | Gabe Black |
| 2011-05-13 | ARM: Construct the predicate test register for more instruction programatically. | Ali Saidi |
| 2011-05-13 | ARM: Further break up condition code into NZ, C, V bits. | Ali Saidi |
| 2011-05-13 | ARM: Remove the saturating (Q) condition code from the renamed register. | Ali Saidi |
| 2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi |
| 2011-04-04 | ARM: Use CPU local lock before sending load to mem system. | Ali Saidi |
| 2011-04-04 | ARM: Cleanup implementation of ITSTATE and put important code in PCState. | Ali Saidi |
| 2011-04-04 | ARM: Fix m5op parameters bug. | Ali Saidi |
| 2011-03-17 | ARM: Rename registers used as temporary state by microops. | Matt Horsnell |
| 2011-01-18 | O3: Fix itstate prediction and recovery. | Matt Horsnell |
| 2010-12-09 | ARM: Take advantage of new PCState syntax. | Gabe Black |
| 2010-12-09 | ARM: Get rid of some unused FP operands. | Gabe Black |
| 2010-12-07 | O3: Make all instructions that write a misc. register not perform the write u... | Giacomo Gabrielli |
| 2010-11-08 | ARM: Add support for M5 ops in the ARM ISA | Ali Saidi |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP access... | Gabe Black |
| 2010-08-25 | ARM: Implement all ARM SIMD instructions. | Gabe Black |
| 2010-06-02 | ARM: Decode to specialized conditional/unconditional versions of instructions. | Gabe Black |
| 2010-06-02 | ARM: Implement the bkpt instruction. | Gabe Black |
| 2010-06-02 | ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. | Gabe Black |
| 2010-06-02 | ARM: Make integer division by zero return a fault. | Gabe Black |
| 2010-06-02 | ARM: Add some support for wfi/wfe/yield/etc | Ali Saidi |
| 2010-06-02 | ARM: Add fp operands to operands.isa. | Gabe Black |
| 2010-06-02 | ARM: Allow flattening into any mode. | Gabe Black |
| 2010-06-02 | ARM: Implement the strex instructions. | Gabe Black |
| 2010-06-02 | ARM: Squash the low order bits of the PC when performing a regular branch. | Gabe Black |
| 2010-06-02 | ARM: When changing the CPSR and branching, make sure the branch is second. | Gabe Black |
| 2010-06-02 | ARM: Explicitly keep track of the second destination for double loads/stores. | Gabe Black |
| 2010-06-02 | ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs. | Gabe Black |
| 2010-06-02 | ARM: Add a base class to support usada8. | Gabe Black |
| 2010-06-02 | ARM: Make LDM that loads the PC perform an interworking branch. | Gabe Black |
| 2010-06-02 | ARM: Align the PC when using it as the base for a load. | Gabe Black |
| 2010-06-02 | ARM: Add support for interworking branch ALU instructions. | Gabe Black |
| 2010-06-02 | ARM: Add an fp version of one of the microop indexed registers. | Gabe Black |
| 2010-06-02 | ARM: Eliminate the unused rhi and rlo operands. | Gabe Black |
| 2010-06-02 | ARM: Implement all integer multiply instructions. | Gabe Black |
| 2010-06-02 | ARM: Implement branch instructions external to the decoder. | Gabe Black |
| 2010-06-02 | ARM: Replace the interworking branch base class with a special operand. | Gabe Black |
| 2010-06-02 | ARM: Fix PC operand handling. | Gabe Black |
| 2010-06-02 | ARM: Add new base classes for data processing instructions. | Gabe Black |
| 2010-06-02 | ARM: Define the load instructions from outside the decoder. | Gabe Black |
