gem5 - gem5

Age	Commit message (Collapse)	Author
2010-06-02	ARM: Make integer division by zero return a fault.	Gabe Black

2010-06-02	ARM: Add some support for wfi/wfe/yield/etc	Ali Saidi

2010-06-02	ARM: Add fp operands to operands.isa.	Gabe Black

2010-06-02	ARM: Allow flattening into any mode.	Gabe Black

2010-06-02	ARM: Implement the strex instructions.	Gabe Black

2010-06-02	ARM: Squash the low order bits of the PC when performing a regular branch.	Gabe Black

2010-06-02	ARM: When changing the CPSR and branching, make sure the branch is second.	Gabe Black

2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black

2010-06-02	ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.	Gabe Black

2010-06-02	ARM: Add a base class to support usada8.	Gabe Black

2010-06-02	ARM: Make LDM that loads the PC perform an interworking branch.	Gabe Black

2010-06-02	ARM: Align the PC when using it as the base for a load.	Gabe Black

2010-06-02	ARM: Add support for interworking branch ALU instructions.	Gabe Black

2010-06-02	ARM: Add an fp version of one of the microop indexed registers.	Gabe Black

2010-06-02	ARM: Eliminate the unused rhi and rlo operands.	Gabe Black

2010-06-02	ARM: Implement all integer multiply instructions.	Gabe Black

2010-06-02	ARM: Implement branch instructions external to the decoder.	Gabe Black

2010-06-02	ARM: Replace the interworking branch base class with a special operand.	Gabe Black

2010-06-02	ARM: Fix PC operand handling.	Gabe Black

2010-06-02	ARM: Add new base classes for data processing instructions.	Gabe Black

2010-06-02	ARM: Define the load instructions from outside the decoder.	Gabe Black

2010-06-02	ARM: Add an operand for accessing the current PC.	Gabe Black

2010-06-02	ARM: Track the current ISA mode using the PC.	Gabe Black

2010-06-02	ARM: Remove IsControl from operands that don't imply control transfers.	Gabe Black
	Also remove IsInteger from CondCodes.
2009-11-14	ARM: More accurately describe the effects of using the control operands.	Gabe Black

2009-11-14	ARM: Hook up the moded versions of the SPSR.	Gabe Black
	These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode.
2009-11-10	ARM: Fix some bugs in the ISA desc and fill out some instructions.	Gabe Black

2009-11-08	ARM: Split the condition codes out of the CPSR.	Gabe Black
	This allows those bits to be renamed while allowing the other fields to control the behavior of the processor.
2009-11-08	ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.	Gabe Black

2009-11-08	ARM: Get rid of the Raddr operand.	Gabe Black

2009-07-27	ARM: Add in spots for the VFP control registers.	Gabe Black

2009-07-27	ARM: Handle register indexed system calls.	Ali Saidi

2009-07-08	ARM: Use custom read/write code to alias R15 with the PC.	Gabe Black

2009-07-08	ARM: Move the integer microops out of the decoder and into the ISA desc.	Gabe Black

2009-07-08	ARM: Add operands for the load/store double instructions.	Gabe Black

2009-06-21	ARM: Get rid of a few more unused operands.	Gabe Black

2009-06-21	ARM: Get rid of unnecessary Re operand.	Gabe Black

2009-06-21	ARM: Pull some static code out of the isa desc and create miscregs.hh.	Gabe Black

2009-04-05	arm: add ARM support to M5	Stephen Hines