| Age | Commit message (Expand) | Author |
|---|---|---|
| 2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi |
| 2011-04-04 | ARM: Cleanup implementation of ITSTATE and put important code in PCState. | Ali Saidi |
| 2011-04-04 | ARM: Tag appropriate instructions as IsReturn | Ali Saidi |
| 2011-03-17 | ARM: Allow conditional quiesce instructions. | Ali Saidi |
| 2011-01-18 | ARM: Add support for moving predicated false dest operands from sources. | Ali Saidi |
| 2010-08-25 | ARM: Use fewer micro-ops for register update loads if possible. | Gene WU |
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong |
| 2010-06-02 | ARM: Decode to specialized conditional/unconditional versions of instructions. | Gabe Black |
| 2010-06-02 | ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. | Gabe Black |
| 2010-06-02 | ARM: Implement data processing instructions external to the decoder. | Gabe Black |
| 2010-06-02 | ARM: Move the templates for predicated instructions into a separate file. | Gabe Black |
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