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path: root/src/arch/arm/isa/templates/pred.isa
AgeCommit message (Expand)Author
2013-03-04ARM: fix some cases where instructions that write to fp reg 15 are accidently...Ali Saidi
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-06-29ARM: Fix identification of one RAS pop instruction.Ali Saidi
2012-03-21ARM: Fix case where cond/uncond control is mis-specifiedNathanael Premillieu
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2010-08-25ARM: Use fewer micro-ops for register update loads if possible.Gene WU
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-06-02ARM: Decode to specialized conditional/unconditional versions of instructions.Gabe Black
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02ARM: Implement data processing instructions external to the decoder.Gabe Black
2010-06-02ARM: Move the templates for predicated instructions into a separate file.Gabe Black