Age | Commit message (Collapse) | Author |
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CLREX is the name of an ARM instruction, not a name for this generic flag.
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Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
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access is disabled.
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when it in received
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THis allows the CPU to handle predicated-false instructions accordingly.
This particular patch makes loads that are predicated-false to be sent
straight to the commit stage directly, not waiting for return of the data
that was never requested since it was predicated-false.
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This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
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This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
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The macroop should never be executed, only it's microops will.
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Fix so it works for older gccs.
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--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
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--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
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This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.
--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
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--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
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