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path: root/src/arch/arm/isa
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2013-05-14arm: Add support for the m5fail pseudo-opAndreas Sandberg
2013-03-04ARM: fix some cases where instructions that write to fp reg 15 are ↵Ali Saidi
accidently branches.
2013-02-19scons: Fix warnings issued by clang 3.2svn (XCode 4.6)Andreas Hansson
This patch fixes the warnings that clang3.2svn emit due to the "-Wall" flag. There is one case of an uninitialised value in the ARM neon ISA description, and then a whole range of unused private fields that are pruned.
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code.
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions.
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
This patch address the most important name shadowing warnings (as produced when using gcc/clang with -Wshadow). There are many locations where constructor parameters and function parameters shadow local variables, but these are left unchanged.
2013-02-15arm: fix some fp comparisons that worked by accident.Ali Saidi
The explict tests in the follwing fp comparison operations were incorrect as they checked for only signaling NaNs and not quite-NaNs as well. When compiled with gcc, the comparison generates a fp exception that causes the FE_INVALID flag to be set and we check for it, so even though the check was incorrect, the correct exception was set. With clang this behavior seems to not occur. The checks are updated to test for nans and the behavior is now correct with both clang and gcc.
2012-12-12arm: set uopSet_uop as conditional or unconditional controlNathanael Premillieu
uopSet_uop is microop instruction that has the IsControl flags set, but the IsCondControl or IsUncondControl flags seems not to be set, neither in the construction nor where the microop is used. This patch adds the the flags in the constructor of the instruction (MicroUopSetPCCPSR). Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
Deletion of the fact that instructions that writes to registers of type "cntrlReg" are not set as control instruction (flag IsControl not set).
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-06-29ARM: Fix identification of one RAS pop instruction.Ali Saidi
The check should be with the op2 field, not with the op1 field.
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
This patch addresses a number of minor issues that cause problems when compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it avoids using the deprecated ext/hash_map and instead uses unordered_map (and similarly so for the hash_set). To make use of the new STL containers, g++ and clang has to be invoked with "-std=c++0x", and this is now added for all gcc versions >= 4.6, and for clang >= 3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1 unordered_map to avoid the deprecation warning. The addition of c++0x in turn causes a few problems, as the compiler is more stringent and adds a number of new warnings. Below, the most important issues are enumerated: 1) the use of namespaces is more strict, e.g. for isnan, and all headers opening the entire namespace std are now fixed. 2) another other issue caused by the more stringent compiler is the narrowing of the embedded python, which used to be a char array, and is now unsigned char since there were values larger than 128. 3) a particularly odd issue that arose with the new c++0x behaviour is found in range.hh, where the operator< causes gcc to complain about the template type parsing (the "<" is interpreted as the beginning of a template argument), and the problem seems to be related to the begin/end members introduced for the range-type iteration, which is a new feature in c++11. As a minor update, this patch also fixes the build flags for the clang debug target that used to be shared with gcc and incorrectly use "-ggdb".
2012-03-21ARM: Fix case where cond/uncond control is mis-specifiedNathanael Premillieu
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-21ARM: IT doesn't need to be serializing.Geoffrey Blake
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2012-03-09ARM: Fix branch prediction issue with CB(N)Z instructionBrian Grayson
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places.
2012-01-31util: implements "writefile" gem5 op to export file from guest to host ↵Dam Sunwoo
filesystem Usage: m5 writefile <filename> File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders.
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification.
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2012-01-07Merge with the main repository again.Gabe Black
2012-01-07Merge with main repository.Gabe Black
2011-12-01ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .Ali Saidi
Squashes the subsequent instructions in O3 pipe after the service call, so that they see the effect of the system call when re-executed. This isn't really an issue with FS mode, but can show up in SE mode. --HG-- extra : rebase_source : 613a69fe1d9834261e25a8cd340aa6b47578e1fe
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
And by "everything" I mean all the quick regressions.
2011-09-26ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.Gabe Black
By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things.
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending.
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
SWP and SWPB now throw an undefined instruction exception if SCTLR.SW == 0. This also required the MIDR to be changed slightly so programs can correctly determine that gem5 supports the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were deprecated, but not disabled at CPU startup).
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason.
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
This change further eliminates cases where condition codes were being read just so they could be written without change because the instruction in question was supposed to preserve them. This is done by creating the condition code code based on the input rather than just doing a simple substitution.
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before.
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags.
2011-05-04ARM: Implement WFE/WFI/SEV semantics.Prakash Ramrakhyani
2011-05-04ARM: Fix small bug with vcvt instructionAli Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help