| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-06-02 | ARM: Decode 16 bit thumb PC relative memory instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode 16 bit thumb immediate addressed memory instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode 16 bit thumb register addressed memory instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make single stores decode to the new external store instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make 32 bit thumb use the new, external load instructions. | Gabe Black | |
| 2010-06-02 | ARM: Define the store instructions from outside the decoder. | Gabe Black | |
| --HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa | |||
| 2010-06-02 | ARM: Define the load instructions from outside the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Create a "decoder" directory for the files implementing the decoder. | Gabe Black | |
| --HG-- rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa | |||
| 2010-06-02 | ARM: Flesh out the 32 bit thumb store single instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the 32 bit thumb load word instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add an operand for accessing the current PC. | Gabe Black | |
| 2010-06-02 | ARM: Flesh out 32 bit thumb load word decoding. | Gabe Black | |
| 2010-06-02 | ARM: Implement some 32 bit thumb data processing immediate instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for 32 bit thumb data processing immediate instructions. | Gabe Black | |
| 2010-06-02 | ARM: Expand the decoding for 32 bit thumb data processing immediate ↵ | Gabe Black | |
| instructions. | |||
| 2010-06-02 | ARM: Stub out the 32 bit Thumb portion of the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Add bitfields for 32 bit thumb. | Gabe Black | |
| 2010-06-02 | ARM: Decode VFP instructions. | Gabe Black | |
| 2010-06-02 | ARM: Stub out the 16 bit thumb decoder. | Gabe Black | |
| 2010-06-02 | ARM: Add thumb bitfields to the ExtMachInst and the isa definition. | Gabe Black | |
| 2010-06-02 | ARM: Make the decoder handle thumb instructions separately. | Gabe Black | |
| --HG-- rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa | |||
| 2010-06-02 | ARM: Add a thumb bit bitfield. | Gabe Black | |
| 2010-06-02 | ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. | Gabe Black | |
| 2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black | |
| 2010-06-02 | ARM: Remove IsControl from operands that don't imply control transfers. | Gabe Black | |
| Also remove IsInteger from CondCodes. | |||
| 2010-03-23 | cpu: fix exec tracing memory corruption bug | Steve Reinhardt | |
| Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes. | |||
| 2009-11-17 | ARM: Begin implementing CP15 | Ali Saidi | |
| 2009-11-17 | ARM: Differentiate between LDM exception return and LDM user regs. | Ali Saidi | |
| 2009-11-16 | imported patch isa_fixes2.diff | Ali Saidi | |
| 2009-11-15 | ARM: Make the exception return form of ldm restore CPSR. | Gabe Black | |
| 2009-11-15 | ARM: Create a new type of load uop that restores spsr into cpsr. | Gabe Black | |
| 2009-11-14 | ARM: Check in the actual change from the last commit. | Gabe Black | |
| The last commit was somehow empty. This was what was supposed to go in it. | |||
| 2009-11-14 | ARM: Fix up the implmentation of the msr instruction. | Gabe Black | |
| 2009-11-14 | ARM: Add a bitfield to indicate if an immediate should be used. | Gabe Black | |
| 2009-11-14 | ARM: Fix up the implmentation of the mrs instruction. | Gabe Black | |
| 2009-11-14 | ARM: More accurately describe the effects of using the control operands. | Gabe Black | |
| 2009-11-14 | ARM: Hook up the moded versions of the SPSR. | Gabe Black | |
| These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode. | |||
| 2009-11-14 | ARM: Move around decoder to properly decode CP15 | Ali Saidi | |
| 2009-11-10 | ARM: Fix some bugs in the ISA desc and fill out some instructions. | Gabe Black | |
| 2009-11-10 | ARM: Implement fault classes. | Gabe Black | |
| Implement some fault classes using the curriously recurring template pattern, similar to SPARCs. | |||
| 2009-11-08 | ARM: Support forcing load/store multiple to use user registers. | Gabe Black | |
| 2009-11-08 | ARM: Simplify the load/store multiple generation code. | Gabe Black | |
| Specifically, get rid of the big switch statement so more cases can be handled. Enumerating all the possible settings doesn't scale well. Also do some minor style clean up. | |||
| 2009-11-08 | ARM: Split the condition codes out of the CPSR. | Gabe Black | |
| This allows those bits to be renamed while allowing the other fields to control the behavior of the processor. | |||
| 2009-11-08 | ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR. | Gabe Black | |
| 2009-11-08 | ARM: Get rid of the Raddr operand. | Gabe Black | |
| 2009-11-08 | ARM: Set up an intregs.hh for ARM. | Gabe Black | |
| Add constants for all the modes and registers, maps for aliasing, functions that use the maps and range check, and use a named constant instead of a magic number for the microcode register. | |||
| 2009-07-29 | ARM: Mul and mla ignore the c and v flags, but we were setting them to 1. | Gabe Black | |
| 2009-07-27 | ARM: Decode fstmx and fldmx instructions. We can ignore them for now. | Gabe Black | |
| 2009-07-27 | ARM: Implement a basic version of the fmxr instruction. | Gabe Black | |
| 2009-07-27 | ARM: Implement a basic version of the fmrx instruction. | Gabe Black | |
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