gem5 - gem5

Age	Commit message (Expand)	Author
2011-08-19	ARM: Add support for DIV/SDIV instructions.	Ali Saidi
2011-08-19	Fix bugs due to interaction between SEV instructions and O3 pipeline	Geoffrey Blake
2011-07-15	ARM: Fix SWP/SWPB undefined instruction behavior	Wade Walker
2011-07-05	ISA parser: Define operand types with a ctype directly.	Gabe Black
2011-07-02	ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.	Gabe Black
2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom
2011-05-18	gcc: fix an uninitialized variable warning from G++ 4.5	Nathan Binkert
2011-05-13	ARM: Generate condition code setting code based on which codes are set.	Ali Saidi
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-05-04	ARM: Implement WFE/WFI/SEV semantics.	Prakash Ramrakhyani
2011-05-04	ARM: Fix small bug with vcvt instruction	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-04	ARM: Use CPU local lock before sending load to mem system.	Ali Saidi
2011-04-04	ARM: Fix bug in MicroLdrNeon templates for initiateAcc().	Ali Saidi
2011-04-04	ARM: Cleanup and small fixes to some NEON ops to match the spec.	William Wang
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-04-04	ARM: Fix m5op parameters bug.	Ali Saidi
2011-04-04	ARM: Tag appropriate instructions as IsReturn	Ali Saidi
2011-03-17	ARM: Fix subtle bug in LDM.	Ali Saidi
2011-03-17	ARM: Identify branches as conditional or unconditional and direct or indirect.	Ali Saidi
2011-03-17	ARM: Fix small bug with VLDM/VSTM instructions.	Ali Saidi
2011-03-17	ARM: Allow conditional quiesce instructions.	Ali Saidi
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
2011-03-17	ARM: Rename registers used as temporary state by microops.	Matt Horsnell
2011-03-17	ARM: Previous change didn't end up setting instFlags, this does.	Ali Saidi
2011-02-23	ARM: NEON instruction templates modified to set the predicate flag to false w...	Giacomo Gabrielli
2011-02-23	ARM: Squash state on FPSCR stride or len write.	Ali Saidi
2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell
2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi
2011-02-23	ARM: Make Noop actually decode to a noop and set it's instflags.	Ali Saidi
2011-02-23	ARM: Adds dummy support for a L2 latency miscreg.	Ali Saidi
2011-01-18	O3: Fix itstate prediction and recovery.	Matt Horsnell
2011-01-18	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	Matt Horsnell
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black
2010-12-09	ARM: Get rid of some unused FP operands.	Gabe Black
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli
2010-11-15	ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...	Ali Saidi
2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-11-08	ARM: Make all ARM uops delayed commit.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black