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path: root/src/arch/arm/isa
AgeCommit message (Collapse)Author
2010-06-02ARM: Add some support for wfi/wfe/yield/etcAli Saidi
2010-06-02ARM: Undef instruction on invalid user CP15 accessAli Saidi
2010-06-02ARM: Decode the VSTR instruction.Gabe Black
2010-06-02ARM: Implement the vstr instruction.Gabe Black
2010-06-02ARM: BXJ should be BX when there is no J supportAli Saidi
2010-06-02ARM: Fix the implementation of the VFP ldm and stm macroops.Gabe Black
There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02ARM: Fix up thumb decoding of coproc instructions.Gabe Black
2010-06-02ARM: Clean up some redundancy and fault behavior for unimplemented thumb ↵Gabe Black
MCR, MRC.
2010-06-02ARM: Decode the VLDR instruction.Gabe Black
2010-06-02ARM: Implement the VLDR instruction.Gabe Black
2010-06-02ARM: Decode all the various forms of vmov.Gabe Black
2010-06-02ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.Gabe Black
2010-06-02ARM: Implement the various versions of VMOV.Gabe Black
2010-06-02ARM: Add a new RegImmOp base class.Gabe Black
2010-06-02ARM: Add a RegRegImmOp base class.Gabe Black
2010-06-02ARM: Widen the immediate fields in the misc instruction classes.Gabe Black
2010-06-02ARM: Add fp operands to operands.isa.Gabe Black
2010-06-02ARM: Decode the VMRS instruction.Gabe Black
2010-06-02ARM: Implement the VMRS instruction.Gabe Black
2010-06-02ARM: Decode the VMSR instruction.Gabe Black
2010-06-02ARM: Implement the VMSR instruction.Gabe Black
2010-06-02ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) ↵Gabe Black
registers.
2010-06-02ARM: Implement the udiv instruction.Gabe Black
2010-06-02ARM: Implement the sdiv instruction.Gabe Black
2010-06-02ARM: Decode the CPS instruction.Gabe Black
2010-06-02ARM: Implement the CPS instruction.Gabe Black
2010-06-02ARM: Decode the SRS instruction.Gabe Black
2010-06-02ARM: Implement the SRS instruction.Gabe Black
2010-06-02ARM: Add a base class for SRS.Gabe Black
2010-06-02ARM: Allow flattening into any mode.Gabe Black
2010-06-02ARM: Decode TBB and TBH.Gabe Black
2010-06-02ARM: Decode the setend instruction.Gabe Black
2010-06-02ARM: Define the setend instruction.Gabe Black
2010-06-02ARM: Make a base class for instructions that use only an immediate.Gabe Black
2010-06-02ARM: Decode the arm version of ldrexd.Gabe Black
2010-06-02ARM: Decode the strex instructions.Gabe Black
2010-06-02ARM: Implement the strex instructions.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.Gabe Black
2010-06-02ARM: Respect the E bit of the CPSR when doing loads and stores.Gabe Black
2010-06-02ARM: Implement the V7 version of alignment checking.Gabe Black
2010-06-02ARM: Decode the RFE instruction.Gabe Black
2010-06-02ARM: Implement the RFE instruction.Gabe Black
2010-06-02ARM: Add a base class for the RFE instruction.Gabe Black
2010-06-02ARM: Make sure some undefined thumb32 instructions fault.Gabe Black
2010-06-02ARM: Squash the low order bits of the PC when performing a regular branch.Gabe Black
2010-06-02ARM: When changing the CPSR and branching, make sure the branch is second.Gabe Black
2010-06-02ARM: Ignore/warn access to the bpimva registers.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the dccmvac register.Gabe Black
2010-06-02ARM: Decode the enterx and leavex instructions.Gabe Black