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path: root/src/arch/arm/isa
AgeCommit message (Expand)Author
2012-06-29ARM: Fix identification of one RAS pop instruction.Ali Saidi
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-03-21ARM: Fix case where cond/uncond control is mis-specifiedNathanael Premillieu
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-21ARM: IT doesn't need to be serializing.Geoffrey Blake
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-09ARM: Fix branch prediction issue with CB(N)Z instructionBrian Grayson
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31util: implements "writefile" gem5 op to export file from guest to host filesy...Dam Sunwoo
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2012-01-07Merge with the main repository again.Gabe Black
2012-01-07Merge with main repository.Gabe Black
2011-12-01ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .Ali Saidi
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
2011-09-26ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.Gabe Black
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-04ARM: Implement WFE/WFI/SEV semantics.Prakash Ramrakhyani
2011-05-04ARM: Fix small bug with vcvt instructionAli Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
2011-04-04ARM: Fix bug in MicroLdrNeon templates for initiateAcc().Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi