| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2011-01-18 | ARM: The ARM decoder should not panic when decoding undefined holes is arch. | Matt Horsnell | |
| This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path. | |||
| 2011-01-18 | ARM: Add support for moving predicated false dest operands from sources. | Ali Saidi | |
| 2010-12-09 | ARM: Take advantage of new PCState syntax. | Gabe Black | |
| 2010-12-09 | ARM: Get rid of some unused FP operands. | Gabe Black | |
| 2010-12-07 | O3: Make all instructions that write a misc. register not perform the write ↵ | Giacomo Gabrielli | |
| until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM). | |||
| 2010-12-07 | O3: Support SWAP and predicated loads/store in ARM. | Min Kyu Jeong | |
| 2010-11-15 | CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. | Giacomo Gabrielli | |
| 2010-11-15 | ARM: Return an FailUnimp instruction when an unimplemented CP15 register is ↵ | Ali Saidi | |
| accessed. Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation. | |||
| 2010-11-15 | ARM: Fix SRS instruction to micro-code memory operation and register update. | Ali Saidi | |
| Previously the SRS instruction attempted to writeback in initiateAcc() which worked until a recent change, but was incorrect. | |||
| 2010-11-08 | ARM: Add support for M5 ops in the ARM ISA | Ali Saidi | |
| 2010-11-08 | ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. | Ali Saidi | |
| This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path. | |||
| 2010-11-08 | ARM: Make all ARM uops delayed commit. | Ali Saidi | |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black | |
| This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. | |||
| 2010-10-22 | ISA: Simplify various implementations of completeAcc. | Gabe Black | |
| 2010-10-22 | ARM: Don't pretend to writeback registers in initiateAcc. | Gabe Black | |
| 2010-10-13 | Mem: Change the CLREX flag to CLEAR_LL. | Gabe Black | |
| CLREX is the name of an ARM instruction, not a name for this generic flag. | |||
| 2010-10-01 | ARM: Clean up use of TBit and JBit. | Ali Saidi | |
| Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code. | |||
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black | |
| Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. | |||
| 2010-08-25 | ARM: Adding a bogus fault that does nothing. | Min Kyu Jeong | |
| This fault can used to flush the pipe, not including the faulting instruction. The particular case I needed this was for a self-modifying code. It needed to drain the store queue and force the following instruction to refetch from icache. DCCMVAC cp15 mcr instruction is modified to raise this fault. | |||
| 2010-08-25 | ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing | Ali Saidi | |
| 2010-08-25 | ARM: Use fewer micro-ops for register update loads if possible. | Gene WU | |
| Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict. | |||
| 2010-08-25 | ARM: Fix VFP enabled checks for mem instructions | Ali Saidi | |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black | |
| 2010-08-25 | ARM: Fix type comparison warnings in Neon. | Gabe Black | |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP ↵ | Gabe Black | |
| access is disabled. | |||
| 2010-08-25 | ARM: Implement all ARM SIMD instructions. | Gabe Black | |
| 2010-08-23 | ARM: Implement DBG instruction that doesn't do much for now. | Gene Wu | |
| 2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches ↵ | Gene Wu | |
| when it in received | |||
| 2010-08-23 | ARM: Don't write tracedata on writes, it might have been freed already. | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX init/complete acc methods | Gene Wu | |
| 2010-08-23 | ARM: Implement DSB, DMB, ISB | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX | Gene Wu | |
| 2010-08-23 | ARM: BX instruction can be contitional if last instruction in a IT block | Gene Wu | |
| Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. | |||
| 2010-08-23 | ARM: mark msr/mrs instructions as SerializeBefore/After | Min Kyu Jeong | |
| Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR | |||
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong | |
| THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false. | |||
| 2010-08-23 | ARM: Temporary local variables can't conflict with isa parser operands. | Gene Wu | |
| PC is an operand, so we can't have a temp called PC | |||
| 2010-08-23 | ARM: Exclusive accesses must be double word aligned | Ali Saidi | |
| 2010-08-23 | ARM: Decode neon memory instructions. | Ali Saidi | |
| 2010-08-23 | ARM: Clean up the ISA desc portion of the ARM memory instructions. | Gabe Black | |
| 2010-08-23 | ARM: Implement some more misc registers | Ali Saidi | |
| 2010-07-15 | ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵ | Gabe Black | |
| fault. | |||
| 2010-06-02 | ARM: Fix IT state not updating when an instruction memory instruction faults. | Min Kyu Jeong | |
| 2010-06-02 | ARM: Decode the neon instruction space. | Gabe Black | |
| 2010-06-02 | ARM: Move some case values out of ##included files. | Gabe Black | |
| This will help keep the high level decode together and not have it spread into the subordinate decode stuff. The ##include lines still need to be on a line by themselves, though. | |||
| 2010-06-02 | ARM: Combine some redundant cases in one of the data decode functions. | Gabe Black | |
| 2010-06-02 | ARM: Get rid of the binary dumping function in utility.hh. | Gabe Black | |
| 2010-06-02 | ARM: Decode to specialized conditional/unconditional versions of instructions. | Gabe Black | |
| This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them. | |||
| 2010-06-02 | ARM: Make sure undefined unconditional ARM instructions decode as such. | Gabe Black | |
| 2010-06-02 | ARM: Implement a version of mcr and mrc that works in user mode. | Gabe Black | |
| 2010-06-02 | ARM: Hook the misc instructions into the thumb decoder. | Gabe Black | |
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