gem5 - gem5

Age	Commit message (Expand)	Author
2012-09-25	ARM: Inst writing to cntrlReg registers not set as control inst	Nathanael Premillieu
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-06-29	ARM: Fix identification of one RAS pop instruction.	Ali Saidi
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-04-14	clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6	Andreas Hansson
2012-03-21	ARM: Fix case where cond/uncond control is mis-specified	Nathanael Premillieu
2012-03-21	ARM: Clean up condCodes in IT blocks.	Ali Saidi
2012-03-21	ARM: IT doesn't need to be serializing.	Geoffrey Blake
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-03-09	ARM: Fix branch prediction issue with CB(N)Z instruction	Brian Grayson
2012-03-01	ARM: Add limited CP14 support.	Matt Horsnell
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	util: implements "writefile" gem5 op to export file from guest to host filesy...	Dam Sunwoo
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-07	Merge with the main repository again.	Gabe Black
2012-01-07	Merge with main repository.	Gabe Black
2011-12-01	ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .	Ali Saidi
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.	Gabe Black
2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
2011-09-26	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	Gabe Black
2011-09-19	PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.	Gabe Black
2011-09-18	Pseudoinst: Add an initParam pseudo inst function.	Gabe Black
2011-09-13	CP15 c15: enable execution with accesses to c15 registers	Chander Sudanthi
2011-08-19	ARM: Add support for DIV/SDIV instructions.	Ali Saidi
2011-08-19	Fix bugs due to interaction between SEV instructions and O3 pipeline	Geoffrey Blake
2011-07-15	ARM: Fix SWP/SWPB undefined instruction behavior	Wade Walker
2011-07-05	ISA parser: Define operand types with a ctype directly.	Gabe Black
2011-07-02	ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.	Gabe Black
2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom
2011-05-18	gcc: fix an uninitialized variable warning from G++ 4.5	Nathan Binkert
2011-05-13	ARM: Generate condition code setting code based on which codes are set.	Ali Saidi
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-05-04	ARM: Implement WFE/WFI/SEV semantics.	Prakash Ramrakhyani
2011-05-04	ARM: Fix small bug with vcvt instruction	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-04	ARM: Use CPU local lock before sending load to mem system.	Ali Saidi
2011-04-04	ARM: Fix bug in MicroLdrNeon templates for initiateAcc().	Ali Saidi
2011-04-04	ARM: Cleanup and small fixes to some NEON ops to match the spec.	William Wang
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-04-04	ARM: Fix m5op parameters bug.	Ali Saidi
2011-04-04	ARM: Tag appropriate instructions as IsReturn	Ali Saidi
2011-03-17	ARM: Fix subtle bug in LDM.	Ali Saidi