| Age | Commit message (Expand) | Author |
|---|
| 2018-04-19 | arch-arm: Change disassemble when MSR to UNKNOWN register | Giacomo Travaglini |
| 2018-04-10 | arch-arm: Fix mrc,mcr to cop14 disassemble | Giacomo Travaglini |
| 2018-03-26 | arch: Fix all override related warnings. | Gabe Black |
| 2018-03-20 | arch, arm: Fix implicit-fallthrough GCC warnings | Chun-Chen Hsu |
| 2018-03-15 | arm: Fix implicit-fallthrough warnings when building with gcc-7+ | Siddhesh Poyarekar |
| 2018-03-14 | arm: Fix maybe-uninitialized GCC warnings | Chun-Chen Hsu |
| 2018-03-14 | arch-arm: ERET from AArch64 to AArch32 ignore MSBs | Giacomo Travaglini |
| 2018-03-06 | arm: Remove ignored const qualifier | Siddhesh Poyarekar |
| 2018-02-20 | arch-arm: Make hlt64 a mem barrier with semihosting | Giacomo Travaglini |
| 2018-02-20 | arch-arm: Add AArch32 HLT Semihosting interface | Giacomo Travaglini |
| 2018-02-20 | arch-arm: Add AArch32 SVC Semihosting interface | Giacomo Travaglini |
| 2018-02-20 | arch-arm: Adding isa templates for semihosting ops | Giacomo Travaglini |
| 2018-02-20 | arch-arm: HLT using immediate when checking for semihosting | Giacomo Travaglini |
| 2018-02-20 | arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly | Giacomo Travaglini |
| 2018-02-19 | arch-arm: Add aarch64 semihosting support | Andreas Sandberg |
| 2018-02-16 | arch-arm: IMPLEMENTATION DEFINED register | Giacomo Travaglini |
| 2018-02-16 | arch-arm: Fix big endian support in {Load,Store}Double64 | Chuan Zhu |
| 2018-02-16 | arch-arm: Decode Brk64 instructions | Andreas Sandberg |
| 2018-02-07 | arch-arm: Change the type of fault for dc ivac instructions | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Unify permission checks for dc * instructions | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Turn dc ivac to dc civac when some conditions are met | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Fix printing of the data cache maintenance instructions | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Fix cache line size for cache maintenace inst | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Change function name for banked miscregs | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix AArch32 SETEND Instruction | Giacomo Travaglini |
| 2018-02-05 | arch-arm: Removing Serializing flag from ISB | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Fixed WFE/WFI trapping behaviour | Giacomo Travaglini |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-05 | arm: Add support for the dc {civac, cvac, cvau, ivac} instr | Nikos Nikoleris |
| 2017-12-05 | arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions | Nikos Nikoleris |
| 2017-11-22 | arch-arm: Add support for the brk instruction | Andreas Sandberg |
| 2017-11-22 | arch-arm: HVC instruction undefined in secure EL1 | Giacomo Travaglini |
| 2017-11-21 | arch-arm: Fix MSR/MRS disassemble | Giacomo Travaglini |
| 2017-11-15 | arch-arm: Dsb instruction shouldn't flush the pipeline | Giacomo Travaglini |
| 2017-11-15 | arch-arm: Removing FlushPipe fault, using SquashAfter | Giacomo Travaglini |
| 2017-11-15 | arm: Add support for armv8 CRC32 instructions | Giacomo Travaglini |
| 2017-11-13 | arch-arm: Corrected encoding for T32 HVC instruction | Giacomo Travaglini |
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
| 2017-10-20 | arch-arm: RBIT instruction using mirroring func | Giacomo Travaglini |
| 2017-10-13 | arch-arm: Signal an event when executing store exclusives | Nikos Nikoleris |
| 2017-08-01 | arch-arm: Use named constants for m5op instructions | Andreas Sandberg |
| 2017-07-13 | arch-arm: fix ldm of pc interswitching branch | Gedare Bloom |
| 2017-07-05 | arch: ISA parser additions of vector registers | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-05-23 | arch-arm: Fix some poorly done type max and min in NEON | Rekai Gonzalez-Alberquilla |
| 2017-05-19 | base, sim, arch: Fix clang 5.0 warnings | Andreas Sandberg |
| 2017-04-03 | arm: Don't panic when checking coprocessor read/write permissions | Nikos Nikoleris |
| 2017-02-21 | arm: Fix DPRINTFs with arguments in the instruction declarations | Nikos Nikoleris |
| 2016-10-15 | cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass | Fernando Endo |
