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path: root/src/arch/arm/isa
AgeCommit message (Expand)Author
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-05-23arch-arm: Fix some poorly done type max and min in NEONRekai Gonzalez-Alberquilla
2017-05-19base, sim, arch: Fix clang 5.0 warningsAndreas Sandberg
2017-04-03arm: Don't panic when checking coprocessor read/write permissionsNikos Nikoleris
2017-02-21arm: Fix DPRINTFs with arguments in the instruction declarationsNikos Nikoleris
2016-10-15cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClassFernando Endo
2016-10-13isa,arm: Add missing AArch32 FP instructionsMitch Hayenga
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
2016-08-02arm: Fix trapping to Hypervisor during MSR/MRS read/writeDylan Johnson
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
2016-06-02arm: Correctly check FP/SIMD access permission in aarch32Andreas Sandberg
2016-05-26arm: Fix heap overflow issue in Neon64Load operationAndreas Hansson
2016-04-13misc: Fix issues flagged by gcc 6Andreas Hansson
2016-02-29arm: Squash after returning from exceptions in v7Mitch Hayenga
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2016-01-07pseudo inst,util: Add optional key to initparam pseudo instructionGabor Dozsa
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-06-09arm: Fix typo in ldrsh instruction nameRune Holm
2015-05-05arm: Add missing FPEXC.EN checkAndreas Hansson
2015-03-02arm: Remove unnecessary dependencies between AArch64 FP instructionsGiacomo Gabrielli
2015-02-16arm: Merge ISA files with pseudo instructionsAndreas Sandberg
2015-01-25arm: always set the IsFirstMicroop flagAli Saidi
2014-12-23arm: Raise an alignment fault if a PC has illegal alignmentAndreas Sandberg
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-10-29arm: Mark some miscregs (timer counter) registers at unverifiable.Ali Saidi
2014-09-02arm: Don't speculatively access most miscregisters.Akash Bagdia
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-10-01arm: More UBSan cleanups after additional full-system runsAndreas Hansson
2014-09-27arm: Fixed undefined behaviours identified by gccAndreas Hansson
2014-09-03arm: Make memory ops work on 64bit/128-bit quantitiesMitch Hayenga
2014-09-03arm: Fix v8 neon latency issue for loads/storesMitch Hayenga
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-09-03arm: ISA X31 destination register fixAndrew Bardsley
2014-09-03arm: Mark v7 cbz instructions as direct branchesMitch Hayenga
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-04-17arm: Make sure UndefinedInstructions are properly initializedAli Saidi
2014-05-09arm: Add branch flags onto macroopsAndrew Bardsley
2014-05-09arm: add preliminary ISA splits for ARM archCurtis Dunham
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
2014-05-09arm: Panics in miscreg read functions can be tripped by O3 modelGeoffrey Blake
2014-05-09arch: remove inline specifiers on all inst constrs, all ISAsCurtis Dunham
2014-05-09arm: cleanup ARM ISA definitionCurtis Dunham
2014-04-23arm: Don't use a stack allocated mnemonicMitchell Hayenga
2014-03-23arm: m5ops readfile64 args broken, offset coming through garbageEric Van Hensbergen
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-05-14arm: Add support for the m5fail pseudo-opAndreas Sandberg