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path: root/src/arch/arm/isa
AgeCommit message (Expand)Author
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15ARM: Fix SRS instruction to micro-code memory operation and register update.Ali Saidi
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-22ISA: Simplify various implementations of completeAcc.Gabe Black
2010-10-22ARM: Don't pretend to writeback registers in initiateAcc.Gabe Black
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
2010-10-01ARM: Clean up use of TBit and JBit.Ali Saidi
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-25ARM: Adding a bogus fault that does nothing.Min Kyu Jeong
2010-08-25ARM: Make VMSR, RFE PC/LR etc non speculative, and serializingAli Saidi
2010-08-25ARM: Use fewer micro-ops for register update loads if possible.Gene WU
2010-08-25ARM: Fix VFP enabled checks for mem instructionsAli Saidi
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-08-25ARM: Fix type comparison warnings in Neon.Gabe Black
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black
2010-08-23ARM: Implement DBG instruction that doesn't do much for now.Gene Wu
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches whe...Gene Wu
2010-08-23ARM: Don't write tracedata on writes, it might have been freed already.Gene Wu
2010-08-23ARM: Implement CLREX init/complete acc methodsGene Wu
2010-08-23ARM: Implement DSB, DMB, ISBGene Wu
2010-08-23ARM: Implement CLREXGene Wu
2010-08-23ARM: BX instruction can be contitional if last instruction in a IT blockGene Wu
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-08-23ARM: Temporary local variables can't conflict with isa parser operands.Gene Wu
2010-08-23ARM: Exclusive accesses must be double word alignedAli Saidi
2010-08-23ARM: Decode neon memory instructions.Ali Saidi
2010-08-23ARM: Clean up the ISA desc portion of the ARM memory instructions.Gabe Black
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-07-15ARM: Make an SRS instruction with a bad mode cause an undefined instruction f...Gabe Black
2010-06-02ARM: Fix IT state not updating when an instruction memory instruction faults.Min Kyu Jeong
2010-06-02ARM: Decode the neon instruction space.Gabe Black
2010-06-02ARM: Move some case values out of ##included files.Gabe Black
2010-06-02ARM: Combine some redundant cases in one of the data decode functions.Gabe Black
2010-06-02ARM: Get rid of the binary dumping function in utility.hh.Gabe Black
2010-06-02ARM: Decode to specialized conditional/unconditional versions of instructions.Gabe Black
2010-06-02ARM: Make sure undefined unconditional ARM instructions decode as such.Gabe Black
2010-06-02ARM: Implement a version of mcr and mrc that works in user mode.Gabe Black
2010-06-02ARM: Hook the misc instructions into the thumb decoder.Gabe Black
2010-06-02ARM: Move some miscellaneous instructions out of the decoder to share with th...Gabe Black
2010-06-02ARM: Treat LDRD in ARM with an odd index as an undefined instruction.Gabe Black