summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa
AgeCommit message (Collapse)Author
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
Change-Id: Ifb9f1db288e401761b71ccf426e370c475e5663f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20622 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
In src/cpu/reg_class.hh, numPinnedWrites was unset because the constructors were not well factored out. Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm: Fix implicit fallthrough build errorsChun-Chen TK Hsu
1942b21713 introduced implicit-fallthrough errors when compiled with GCC 8. This change adds M5_UNREACHABLE in the default case. Change-Id: I220f2b3fe39b5c3a65c0dd390915bffeafb28962 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20268 Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12arch-arm: Added LD/ST<op> atomic instruction family and SWP instrsJordi Vaquero
Adding LD/ST/SWP family of instructions, LD/ST include a set of operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN This commit includes: + Instruction decode + Instruction functional code + New set of skeletons for Ex/Com/Ini/Constructor and declaration. Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-08-12arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic funcJordi Vaquero
CAS/CASP atomic instruction implementation This change includes: + Instructions decode + new amo64.isa file where CAS/CASP main functional code is implemented + mem64.isa include Execute/complete/initiatie skeletons, contructor and declarator + Added TypedAtomic function for pair register CASP instruction Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19811 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-08-05arch-arm: Implement ARMv8.1-PAN, Privileged access neverGiacomo Travaglini
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state bit is 1, any privileged data access from EL1 or EL2 to a virtual memory address that is accessible at EL0 generates a Permission fault. This feature is mandatory in ARMv8.1 implementations. This feature is supported in AArch64 and AArch32 states. The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields identify the support for ARMv8.1-PAN. Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I94a76311711739dd2394c72944d88ba9321fd159 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-05arch-arm: Rewrite MSR immediate instruction classGiacomo Travaglini
MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Fix reg dependency for SVE gather microopsGabor Dozsa
The first microop of an SVE gather creates a copy of the source vecreg into AA64FpUreg0. The subsequent microops must refer to this copy as a source in order to establish the correct register dependencies. Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19172 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Fix tracing code for SVE gatherGabor Dozsa
Printing the entire contents of the dest vecreg for each gather microop is suboptimal as it creates false positive differences between Atomic and O3 traces. This fix prints only the memory data which a microop loads from memory. Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19171 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Add SVE LD1RQ[BHWD]Javier Setoain
Add both scalar+scalar and scalar+immediate versions. Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-27arch-arm: Fix decoding for SVE memory instructionsAdrià Armejach
Some SVE memory instructions are missing the makeSP function for register operands that can be the SP register. This leads to segmentation faults on the application side as the wrong register is decoded. Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19169 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-07-27arch-arm: Add support for SVE load/store structuresJavier Setoain
Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-18arch-arm: Add first-/non-faulting load instructionsGabor Dozsa
First-/non-faulting loads are part of Arm SVE. Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-17arch-arm: Move the memacc_code before op_wb in fp loadsGiacomo Travaglini
This is trying to fix the bug that arises when a memory exception is generated during a fp flavoured load (A memory load targeting a SIMD & FP register). With the previous template a fault was not stopping the register value to be modified (wrong) if (fault == NoFault) { fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } if (fault == NoFault) { %(op_wb)s; } The patch introduces a Load64FpExecute template which is moving the register write (memacc_code) just before the op_wb Change-Id: I1c89c525dfa7a4ef489abe0872cd7baacdd6ce3c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10arch-arm: implement VMINNM scalar thumbCiro Santilli
VMINNM was implemented at Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 but the thumb scalar encoding was missing. This patch implements it. Change-Id: Ia29ec77dbd82f6be6b3d040a0e737794f52c33bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19108 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31arm: Fix decoding of CRC32 instructions in thumb32Chun-Chen TK Hsu
The CRC32 and CRC32C instructions are incorrectly decoded in thumb32 mode according to the latest manual: https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578 Signed-off-by: Chun-Chen TK Hsu Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31arch-arm: Treat SVE prefetch instructions as no-opsGiacomo Gabrielli
Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13522 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch-arm: Add initial support for SVE gather/scatter loads/storesGiacomo Gabrielli
Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13521 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-23arch-arm: Change mcrMrc15TrapToHyp signatureGiacomo Travaglini
This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp helper function. Rather than passing registers as arguments, we are just passing a ThreadContext pointer Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM scalar versionCiro Santilli
ARMv8.2 16-bit versions have not yet been implemented, but a placeholders were created for them. Refactor the nearby decoding tree to closely match the ARM spec A32 decode table. That piece of the tree can also be called from thumb which decodes it in the same way, although the thumb decode table has a different terminology The old code didn't match neither A32 or T32 terminologies, so it is better to at least match one of them to help verify correctness. Change-Id: Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18690 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM SIMD versionCiro Santilli
This instruction is backported from aarch64. In order to use the existing fplibMinNum backend, we first move VMIN and VPMIN to use fplib. Adding VMINNM is then trivial. Change-Id: I404daabeb6079f60e51a648a06d5b3e54f1c24a9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: rename operands to match spec in isa/formats/fp.isaCiro Santilli
Matches ARM DDI 0487D.a decoding tables. Change-Id: I48338ef956a04308d55d1022229ebe0962a8fe5d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18688 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-11arch-arm: Add initial support for SVE contiguous loads/storesGiacomo Gabrielli
Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution of bugfixes. Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
We know for sure what the ISA is, so there's no need for the indirection. Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
Clang with -Wconstant-conversion is _very_ restrictive on casting. The shift operator results in an incorrect promotion. This patch add a compile-time static cast that remove the error when clang is used. Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28arch-arm: Fix use of bitwise operators on booleansJavier Setoain
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28arch-arm: Fix index generation for VecElem operandsGiacomo Travaglini
Current operand generation is not providing VecElems with the right vector index and element index. The bug was covered when registers were 128 bit wide, but with SVE we have augmented the vector register size and the bug has been exposed. E.g. With dest = 2, FpDestP2 = (vec_index = 0, elem_index = 4) whereas it should be FpDestP2 = (vec_index = 1, elem_index = 0) Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710
2019-03-25arch-arm: Add missing fall-through defaultsJavier Setoain
Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain <javier.setoain@arm.com> - Gabor Dozsa <gabor.dozsa@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com> Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-11arch-arm: Fixing implicit fallthrough build errorsRyan Gambord
2c242d6 introduced implicit-fallthrough errors when building against ARM. Added "default: return new Unknown(machInst);" to offending switch statements; please verify this is the corret behavior Signed-off-by: Ryan Gambord Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-01arch-arm: implement floating point aarch32 VCVTA familyCiro Santilli
These instructions round floating point to integer, and were added to aarch32 as an extension to ARMv7. Change-Id: I62d1705badc95a4e8954a5ad62b2b6bc9e4ffe00 Reviewed-on: https://gem5-review.googlesource.com/c/16788 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove floatReg operand typeGiacomo Travaglini
Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15604 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Use VecElem instead of FloatReg for FP instructionGiacomo Travaglini
SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in AArch64 mode. The usage of two different register pools breaks interprocessing between A32 and A64. This patch is changing definition of arm operands so that they are backed by VecElems in A32, which are mapped to the same storage as A64 VecRegs. Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217 Reviewed-on: https://gem5-review.googlesource.com/c/15603 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove unused float operandsGiacomo Travaglini
Removing FaP1 and FDest2 since they are not currently used by any ARM instruction. Change-Id: I4251dfcdd3f4434caaf0bdab507c1c3bd53fb5d2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15596 Reviewed-by: Ciro Santilli <ciro.santilli@gmail.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
This patch is implementing LoadAcquire/StoreRelease instructions in AArch32, which were added in ARMv8-A only and where not present in ARMv7. Change-Id: I5e26459971d0b183a955cd7b0c9c7eaffef453be Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15817 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: IsStoreConditional flag set depending on flavorGiacomo Travaglini
This patch is aligning A32 with A64 where the IsStoreConditional flag doesn't have to be specified manually in the instruction implementation, but will be automatically added to any exclusive store. Change-Id: Id02ed6fc2beeca6d125017393714a7c6eb3d8a33 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15816 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-14arm: Stop using the FloatReg and FloatRegBits types.Gabe Black
This will let us make those types 64 bits to be in line with the other architectures. Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021 Reviewed-on: https://gem5-review.googlesource.com/c/13621 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-10-26arch-arm: We add PRFM PST instruction for armyuetsu.kodama
Note current PRFM supports only PLD, but PST (prefetch for store) is also important for latency hiding. We also bug fix in disassembler to display prfop correctly. Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13 Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp> Reviewed-on: https://gem5-review.googlesource.com/c/13675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPLGiacomo Travaglini
While there is a AArch32 class for instructions accessing implementation defined registers, we are lacking for the AArch64 counterpart. we were relying on FailUnimplemented, which is untrappable at EL2 (except for HCR_EL2.TGE) since it is just raising Undefined Instruction. Change-Id: I923cb914658ca958af031612cf005159707b0b4f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13779 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Refactor AArch64 MSR/MRS trappingGiacomo Travaglini
This patch refactors AArch64 MSR/MRS trapping, by moving the trapping helpers in arch/arm/utility and in the isa code into a MiscRegOp64 class. This class is the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. The common denominator or those instruction is the chance that the system register access is trapped to an upper Exception level. MiscRegOp64 is providing that feature. What do we gain? Other "pseudo" instructions, like access to implementation defined registers can inherit from this class to make use of the trapping functionalities even if there is no data movement between GPRs and system register. Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13778 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Trap to EL2 only if not in Secure StateGiacomo Travaglini
MRS/MSR Instructions should trap to EL2 only if we are in non-Secure state since at the current implementation (Armv8.0) there is no Secure EL2. Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13777 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Fix HVC trapping beahviourGiacomo Travaglini
This patch is fixing HVC trapping behaviour, reusing the pseudocode implementation provided in the arm arm. Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13776 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-19arm: treat aarch64 hints as NOPs instead of panicCiro Santilli
Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13476 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-19arm: update hint instruction decoding to match ARMv8.5Ciro Santilli
This fixes: - unallocated hints that have since been allocated - unallocated and unimplemented hint instructions being treated as Unknown instead of the correct NOP - missing encoding for DBG on A32 Unallocated and unimplemented hints give a warning if executed. The most important fix was for the CSDB Spectre mitigation instruction, which was added recently and previously unallocated and treated as Unknown. The Linux kernel v4.18 ARMv7 uses CSDB it and boot would fail with "undefined instruction" since Linux commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13475 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch64 Crypto AESGiacomo Travaglini
This patch implements the AArch64 AES instructions from the Crypto extension. Change-Id: I9143041ec7e1c6a50dcad3f72d7d1b55d6f2d402 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13250 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch64 Crypto SHAGiacomo Travaglini
This patch implements the AArch64 secure hashing instructions from the Crypto extension. Change-Id: I2cdfa81b994637c880f2523fe37cdc6596d05cb1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13249 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch32 Crypto AESMatt Horsnell
This patch implements the AArch32 AES instructions from the Crypto extension. Change-Id: I51e6deda748b0c26135bcfe9d0c7128f3af91f3d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Matt Horsnell <matt.horsnell@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13248 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-11 09:00:56 +0000