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This isn't used by anything any more. The func field is left in place
to ensure compatability, but there's no reason to decode a value
nobody is going to use.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187
Change-Id: I85fcd0e4a362551c29af6bff350d99af86050415
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23179
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Right now, there are only two places which call the pseudoInst function
directly, the ARM KVM CPU and the generic mmapped IPR. These two
callers currently use the generic "PseudoInstABI" which is just a
wrapper around the existing getArgument function.
In the future, this getArgument function will be disolved, and the
PseudoInstABI will be defined for each ABI. Since it currently mimics
the Linux ABI since gem5 can only handle one ABI at a time right now,
this implementation will probably be shared by linux system calls,
except that the pseudo inst implementation will eat return values since
those are returned through other means when the pseudo inst is based on
magic address ranges.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187
Change-Id: Ied97e4a968795158873e492289a1058c8e4e411b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23178
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)
Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>
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The exact mapping of the KVM registers and the gem5 registers is direct and
may not actually be correct.
Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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The methods which set or get an attribute from the virtual GIC use a
shift constant which is 32, but they store their result in a 32 bit
variable and, according to clang, are used to shift 32 bit inputs. This
is undefined behavior in terms of the shift, and will truncate off the
value regardless.
Change-Id: Ie9543ab9e6e1d5f86317a9210d220928b23ffaf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23129
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Those registers are 32-bit instead of 64 in the KVM API.
The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains:
0x6020 0000 0010 00d4 FPSR 32 fp_regs.fpsr
0x6020 0000 0010 00d5 FPCR 32 fp_regs.fpcr
The register itself is 64-bit in the ARM manual, but the top 32 are
RES0.
This fixes the following error when running ARM KVM early in the
simulation:
panic: KVM: Failed to set register (0x60300000001000d4) value
(errno: 22)
Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I31bd3563c2427efd7e520f714b1ca6f480fa4e85
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This will let us make those types 64 bits to be in line with the other
architectures.
Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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The Pl390 model has evolved and acquired a lot of the features from GICv2,
which means that the name is no longer appropriate. Rename it to GICv2
since this is more representative of the supported features.
GICv2 is backwards compatible with the older Pl390, so we decided to
simply rename the class to represent both GICv2 and older interfaces such
as the instead of creating a new separate one.
Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12492
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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A System object has a _numContexts member variable which represent the
number of ThreadContext registered in the System. Since this has to
match the size of the ThreadContext vector, this patch removes the
manually cached size. This was usually used as a for-loop index, whereas
we want to enforce the use of range-based loops whenever possible.
Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8062
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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The MuxingKvmGic class defined a few functions related to checkpointing which
did nothing other than call the underlying Pl390 implementation. These are
unnecessary in general, and are particularly unnecessary for the loadState
function which is a very lightly used part of the checkpointing interface.
It's not actually defined in Pl390 either, and falls through to the
underlying implementation.
Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff
Reviewed-on: https://gem5-review.googlesource.com/4760
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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ISA devices typically run in the device event queue. Previously, we
assumed that devices would perform their own EQ migrations as
needed. This isn't ideal since it means we have different conventions
for IO devices and ISA devices. Switch to doing migrations in the KVM
CPU instead to make the behavior consistent.
Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4288
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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If an interrupt was pending according to Kvm state during a drain,
the Pl390 model would create an interrupt event that could not be
serviced, preventing the system from draining. The proper behavior
is for the Pl390 not actively being used for simulation to just skip
the GIC state machine that delivers interrupts.
Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ
signals from gem5's simulated GIC to KVM. However, these signals
shouldn't be used when the in-kernel GIC emulator is used.
Instead of delivering the interrupts to the guest, we should just
ignore them since any such pending interrupts are likely to be an
artifact of CPU switching or incorrect draining.
Change-Id: I083b72639384272157f92f44a6606bdf0be7413c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3660
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The ARM MiscRegs implementation has two interfaces: 'normal'
and 'no effect'. The latter acts as a way to access the
backing store without architectural 'effects'. For instance,
a normal write to a timer compare value would call into the
timer model to emulate the device. The 'no effect' interface,
however, would just write the value into the register backing
store and do nothing else.
For Kvm execution, a delicate balance must be struck for the
timer device specifically. We need the code in the model
to be run, because it contains state other than the register
backing store that must stay in sync. On the other hand, we
don't necessarily want the timer model to schedule gem5
events when this happens.
In this commit, we ensure that we use the 'effectful'
MiscReg interface when copying the CP15 timer registers
from Kvm back into gem5. The prior commit makes sure
that this doesn't generate unnecessary timer events
or interrupts.
Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9
Reviewed-on: https://gem5-review.googlesource.com/3543
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The check was nearly completely generic anyway,
with the exception of the Kvm CPU type.
This will make it easier for other parts of the
codebase to do similar checks.
Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da
Reviewed-on: https://gem5-review.googlesource.com/3540
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The state transfer code wasn't reading back PSTATE correctly from the
CPU prior to updating the thread context and was incorreclty writing
the register as a 32-bit value when updating KVM. Correctly read back
the state before updating gem5's view of PSTATE and cast the value to
a uint64_t.
Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2963
Reviewed-by: Rahul Thakur <rjthakur@google.com>
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This also allows checkpointing of a Kvm GIC via the Pl390 model.
Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2444
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
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The kernel and gem5 derive MPIDR values from CPU IDs in slightly
different ways. This means that guests running in a multi-CPU setup
sometimes fail to bring up secondary CPUs. Fix this by overriding the
MPIDR value in virtual CPUs just after they have been instantiated.
Change-Id: I916d44978a9c855ab89c80a083af45b0cea6edac
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2461
Reviewed-by: Weiping Liao <weipingliao@google.com>
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1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
when running 32-bit OS
2) Correctly map 64-bit registers to banked 32-bit ones
Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Reviewed-on: https://gem5-review.googlesource.com/2261
Maintainer: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.
Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Reviewed-on: https://gem5-review.googlesource.com/2260
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Maintainer: Rahul Thakur <rjthakur@google.com>
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KvmGic functionality has been subsumed within the new MuxingKvmGic
model, which has Pl390 fallback when not using KVM for fast emulation.
This simplifies configuration and will enable checkpointing between
KVM emulation and full-system simulation.
Change-Id: Ie61251720064c512843015c075e4ac419a4081e8
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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This device allows us to, when KVM support is detected and compiled in,
instantiate the same Gic device whether the actual simulation is with
KVM cores or simulated cores. Checkpointing is not yet supported.
Change-Id: I67e4e0b6fb7ab5058e52c933f4f3d8e7ab24981e
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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A KVM VM is typically a child of the System object already, but for
solving future issues with configuration graph resolution, the most
logical way to keep track of this object is for it to be an actual
parameter of the System object.
Change-Id: I965ded22203ff8667db9ca02de0042ff1c772220
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Add support for overriding the number of interrupt lines in the ARM
KvmGic.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Factor out the kernel device wrapper from the KvmGIC and put it in a
separate class. This will simplify a future kernel/gem5 hybrid GIC.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Result of running 'hg m5style --skip-all --fix-control -a'.
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The checkpoint changes, along with the SMT patches have changed a
number of APIs. Adapt the ArmKvmCPU accordingly.
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This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
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Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.
* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).
* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.
* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
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This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:
* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.
* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.
* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).
* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
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This changeset adds a GIC implementation that uses the kernel's
built-in support for simulating the interrupt controller. Since there
is currently no support for state transfer between gem5 and the
kernel, the device model does not support serialization and CPU
switching (which would require switching to a gem5-simulated GIC).
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This changeset moves the ARM-specific KVM CPU implementation to
arch/arm/kvm/. This change is expected to keep the source tree
somewhat cleaner as we start adding support for ARMv8 and KVM
in-kernel interrupt controller simulation.
--HG--
rename : src/cpu/kvm/ArmKvmCPU.py => src/arch/arm/kvm/ArmKvmCPU.py
rename : src/cpu/kvm/arm_cpu.cc => src/arch/arm/kvm/arm_cpu.cc
rename : src/cpu/kvm/arm_cpu.hh => src/arch/arm/kvm/arm_cpu.hh
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