| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2012-02-24 | MEM: Make port proxies use references rather than pointers | Andreas Hansson | |
| This patch is adding a clearer design intent to all objects that would not be complete without a port proxy by making the proxies members rathen than dynamically allocated. In essence, if NULL would not be a valid value for the proxy, then we avoid using a pointer to make this clear. The same approach is used for the methods using these proxies, such as loadSections, that now use references rather than pointers to better reflect the fact that NULL would not be an acceptable value (in fact the code would break and that is how this patch started out). Overall the concept of "using a reference to express unconditional composition where a NULL pointer is never valid" could be done on a much broader scale throughout the code base, but for now it is only done in the locations affected by the proxies. | |||
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson | |
| Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh | |||
| 2011-10-22 | SE: move page allocation from PageTable to Process | Steve Reinhardt | |
| PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable. The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process. | |||
| 2011-10-22 | syscall_emul: implement MAP_FIXED option to mmap() | Steve Reinhardt | |
| 2011-08-19 | ARM: Mark some variables uncacheable until boot all CPUs are enabled. | Ali Saidi | |
| There are a set of locations is the linux kernel that are managed via cache maintence instructions until all processors enable their MMUs & TLBs. Writes to these locations are manually flushed from the cache to main memory when the occur so that cores operating without their MMU enabled and only issuing uncached accesses can receive the correct data. Unfortuantely, gem5 doesn't support any kind of software directed maintence of the cache. Until such time as that support exists this patch marks the specific cache blocks that need to be coherent as non-cacheable until all CPUs enable their MMU and thus allows gem5 to boot MP systems with caches enabled (a requirement for booting an O3 cpu and thus an O3 CPU regression). | |||
| 2011-05-04 | ARM: Add support for loading the a bootloader and configuring parameters for it | Ali Saidi | |
| 2011-04-20 | fix some build problems from prior changesets | Nathan Binkert | |
| 2011-04-15 | includes: sort all includes | Nathan Binkert | |
| 2011-04-10 | ARM: Fix checkpoint restoration in ARM_SE. | Ali Saidi | |
| 2011-04-10 | ARM: Get rid of some comments/todos that no longer apply. | Ali Saidi | |
| 2011-03-17 | ARM: Add minimal ARM_SE support for m5threads. | Chris Emmons | |
| Updated some of the assembly code sequences to use armv7 instructions and coprocessor 15 for storing the TLS pointer. | |||
| 2011-03-17 | ARM: Detect and skip udelay() functions in linux kernel. | Ali Saidi | |
| This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed. | |||
| 2010-12-20 | Style: Replace some tabs with spaces. | Gabe Black | |
| 2010-11-08 | ARM: Add checkpointing support | Ali Saidi | |
| 2010-11-08 | sim: Use forward declarations for ports. | Ali Saidi | |
| Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything. | |||
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black | |
| This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. | |||
| 2010-08-23 | ARM: Add system for ARM/Linux and bootstrapping | Ali Saidi | |
| 2010-06-02 | ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all | Ali Saidi | |
| Spec2k benchmarks seem to run with atomic or timing mode simple CPUs. Fixed up some constants, handling of 64 bit arguments, and marked a few more syscalls ignoreFunc. | |||
| 2010-06-02 | ARM: fix sizes of structs for ARM Linux | Ali Saidi | |
| 2010-06-02 | ARM: Fixup native trace support and add some v7/recent stack code | Ali Saidi | |
| 2010-06-02 | ARM: Implement the getrusage syscall. | Ali Saidi | |
| 2010-06-02 | ARM: Allow ARM processes to start in Thumb mode. | Gabe Black | |
| 2009-10-30 | Syscalls: Make system calls access arguments like a stack, not an array. | Gabe Black | |
| When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. | |||
| 2009-10-24 | syscall: Addition of an ioctl command code for Power. | Timothy M. Jones | |
| 2009-09-15 | Syscalls: Implement sysinfo() syscall. | Vince Weaver | |
| 2009-07-29 | ARM: Fix an instruction in the cmpxchg kernel provided routine. | Gabe Black | |
| The instruction was encoded as a load instead of the intended store. | |||
| 2009-07-29 | ARM: Get rid of a stray line in the set_tls handler. | Gabe Black | |
| 2009-07-29 | ARM: Ignore the "times" system call. | Ali Saidi | |
| 2009-07-29 | ARM: Fix an ioctl constant. | Ali Saidi | |
| 2009-07-27 | ARM: Update some syscall constants and delete others that are Alpha only. | Ali Saidi | |
| 2009-07-27 | ARM: Fix fstat/fstat64 structs to match EABI definitions. | Ali Saidi | |
| 2009-07-27 | ARM: Handle register indexed system calls. | Ali Saidi | |
| 2009-07-14 | ARM: Fix the "open" flag constants. | Jack Whitham | |
| 2009-06-09 | ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall ↵ | Gabe Black | |
| params. | |||
| 2009-06-09 | ARM: Add a memory_barrier function to the "comm page". | Gabe Black | |
| This function doesn't actually provide a memory barrier (I don't think they're implemented) and instead just returns. | |||
| 2009-06-09 | ARM: Add a cmpxchg implementation to the "comm page". | Gabe Black | |
| This implementation does what it's supposed to (I think), but it's not atomic and doesn't have memory barriers like the kernel's version. | |||
| 2009-06-09 | ARM: Implement TLS. This is not tested. | Gabe Black | |
| 2009-06-09 | ARM: Make ArmLinuxProcess understand "ARM private" system calls. | Gabe Black | |
| 2009-06-09 | ARM: Update the kernel version M5 reports to 2.6.16.19 | Gabe Black | |
| 2009-04-06 | Merge ARM into the head. ARM will compile but may not actually work. | Gabe Black | |
| 2009-04-05 | arm: add ARM support to M5 | Stephen Hines | |
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