Age | Commit message (Collapse) | Author | |
---|---|---|---|
2011-02-23 | ARM: Adds dummy support for a L2 latency miscreg. | Ali Saidi | |
2011-01-18 | ARM: The ARM decoder should not panic when decoding undefined holes is arch. | Matt Horsnell | |
This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path. | |||
2010-08-23 | ARM: Implement some more misc registers | Ali Saidi | |
2010-06-02 | ARM: Some TLB bug fixes. | Ali Saidi | |
2010-06-02 | ARM: Move Miscreg functions out of isa.hh | Ali Saidi | |
2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi | |
2010-06-02 | ARM: Convert the CP15 registers from MPU to MMU. | Gabe Black | |
2010-06-02 | ARM: Implement a function to decode CP15 registers to MiscReg indices. | Gabe Black | |