gem5 - gem5

Age	Commit message (Collapse)	Author
2012-05-10	gem5: Fix a number of incorrect case statements	Ali Saidi

2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
	This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2012-03-01	ARM: Add limited CP14 support.	Matt Horsnell
	New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
	This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places.
2011-09-13	CP15 c15: enable execution with accesses to c15 registers	Chander Sudanthi
	Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13	ARM: Implement numcpus bits in L2CTLR register.	Daniel Johnson

2011-02-23	ARM: Adds dummy support for a L2 latency miscreg.	Ali Saidi

2011-01-18	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	Matt Horsnell
	This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path.
2010-08-23	ARM: Implement some more misc registers	Ali Saidi

2010-06-02	ARM: Some TLB bug fixes.	Ali Saidi

2010-06-02	ARM: Move Miscreg functions out of isa.hh	Ali Saidi

2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi

2010-06-02	ARM: Convert the CP15 registers from MPU to MMU.	Gabe Black

2010-06-02	ARM: Implement a function to decode CP15 registers to MiscReg indices.	Gabe Black