index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
arm
/
miscregs.cc
Age
Commit message (
Expand
)
Author
2012-05-10
gem5: Fix a number of incorrect case statements
Ali Saidi
2012-03-19
gcc: Clean-up of non-C++0x compliant code, first steps
Andreas Hansson
2012-03-01
ARM: Add limited CP14 support.
Matt Horsnell
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2011-09-13
CP15 c15: enable execution with accesses to c15 registers
Chander Sudanthi
2011-09-13
ARM: Implement numcpus bits in L2CTLR register.
Daniel Johnson
2011-02-23
ARM: Adds dummy support for a L2 latency miscreg.
Ali Saidi
2011-01-18
ARM: The ARM decoder should not panic when decoding undefined holes is arch.
Matt Horsnell
2010-08-23
ARM: Implement some more misc registers
Ali Saidi
2010-06-02
ARM: Some TLB bug fixes.
Ali Saidi
2010-06-02
ARM: Move Miscreg functions out of isa.hh
Ali Saidi
2010-06-02
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
Ali Saidi
2010-06-02
ARM: Convert the CP15 registers from MPU to MMU.
Gabe Black
2010-06-02
ARM: Implement a function to decode CP15 registers to MiscReg indices.
Gabe Black