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path: root/src/arch/arm/miscregs.cc
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2017-04-03arm: Don't panic when checking coprocessor read/write permissionsNikos Nikoleris
Instructions that use the coprocessor interface check the current program status to determine whether the current context has the priviledges to read from/write to the coprocessor. Some modes allow the execution of coprocessor instructions, some others do not allow it, while some other modes are unexpected (e.g., executing an AArch32 instruction while being in an AArch64 mode). Previously we would unconditionally trigger a panic if we were in an unexpected mode. This change removes the panic and replaces it with an Undefined Instruction fault that triggers if and when a coprocessor instruction commits in an unexpected mode. This allows speculative coprocessor instructions from unexpected modes to execute but prevents them from gettting committed. Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2281 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-12-19arm: miscreg refactoringCurtis Dunham
Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson
During host bootup, KVM reads/writes to CNTHCTL_EL2. Because this miscreg has not been implemented, the simulation would end there. This patch causes the simulation to warn about the read/write instead of fail. Change-Id: If034bfd0818a9a5e50c5fe86609e945258c96fa3
2016-08-02arm: enable EL2 supportCurtis Dunham
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
2015-05-26arm: implement the CONTEXTIDR_EL2 system reg.Curtis Dunham
2015-05-23dev, arm: Add virtual timers to the generic timer modelAndreas Sandberg
The generic timer model currently does not support virtual counters. Virtual and physical counters both tick with the same frequency. However, virtual timers allow a hypervisor to set an offset that is subtracted from the counter when it is read. This enables the hypervisor to present a time base that ticks with virtual time in the VM (i.e., doesn't tick when the VM isn't running). Modern Linux kernels generally assume that virtual counters exist and try to use them by default.
2015-05-05arm: enable DCZVA by default in SE modeGiacomo Gabrielli
2014-12-08arm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0Andreas Sandberg
The aarch64 system register decoder is currently not decoding PMXEVTYPER_EL0 and PMCCFILTR_EL0 correctly. This changeset updates the decoder so that they are decoded using the values in table C5-6 in ARM DDI 0478A.c.
2014-10-29arm: Mark some miscregs (timer counter) registers at unverifiable.Ali Saidi
The checker can't verify timer registers, so it should just grab the version from the executing CPU, otherwise it could get a larger value and diverge execution.
2014-09-02arm: Don't speculatively access most miscregisters.Akash Bagdia
Speculative exeuction can cause panics in detailed execution mode that shouldn't happen.
2014-10-01arm: Use MiscRegIndex rather than int when flatteningAndreas Hansson
Some additional type checking to avoid future issues.
2014-08-13arm: change MISCREG_L2ERRSR to warn not failDam Sunwoo
Some newer binaries compiled for Versatile Express TC2 contain access to implementation specific L2MERRSR registers. This causes an infinite loop of undefined exceptions. This patch changes the behavior to "warn not fail" to keep the workloads going.
2014-05-09arm: Panics in miscreg read functions can be tripped by O3 modelGeoffrey Blake
Unimplemented miscregs for the generic timer were guarded by panics in arm/isa.cc which can be tripped by the O3 model if it speculatively executes a wrong path containing a mrs instruction with a bad miscreg index. These registers were flagged as implemented and accessible. This patch changes the miscreg info bit vector to flag them as unimplemented and inaccessible. In this case, and UndefinedInst fault will be generated if the register access is not trapped by a hypervisor.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier in arch/arm/kernel/thumbee.c. The Linux kernel code just seems to be saving and restoring the register. This patch adds support for the TEEHBR cp14 register. Note, this may be a special case when restoring from an image that was run on a system that supports ThumbEE.
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places.
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path.
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Move Miscreg functions out of isa.hhAli Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Convert the CP15 registers from MPU to MMU.Gabe Black
2010-06-02ARM: Implement a function to decode CP15 registers to MiscReg indices.Gabe Black