gem5 - gem5

Age	Commit message (Expand)	Author
2014-10-29	arm: Mark some miscregs (timer counter) registers at unverifiable.	Ali Saidi
2014-09-02	arm: Don't speculatively access most miscregisters.	Akash Bagdia
2014-10-01	arm: Use MiscRegIndex rather than int when flattening	Andreas Hansson
2014-08-13	arm: change MISCREG_L2ERRSR to warn not fail	Dam Sunwoo
2014-05-09	arm: Panics in miscreg read functions can be tripped by O3 model	Geoffrey Blake
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-10-31	ARM: add support for TEEHBR access	Chander Sudanthi
2012-05-10	gem5: Fix a number of incorrect case statements	Ali Saidi
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-03-01	ARM: Add limited CP14 support.	Matt Horsnell
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2011-09-13	CP15 c15: enable execution with accesses to c15 registers	Chander Sudanthi
2011-09-13	ARM: Implement numcpus bits in L2CTLR register.	Daniel Johnson
2011-02-23	ARM: Adds dummy support for a L2 latency miscreg.	Ali Saidi
2011-01-18	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	Matt Horsnell
2010-08-23	ARM: Implement some more misc registers	Ali Saidi
2010-06-02	ARM: Some TLB bug fixes.	Ali Saidi
2010-06-02	ARM: Move Miscreg functions out of isa.hh	Ali Saidi
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi
2010-06-02	ARM: Convert the CP15 registers from MPU to MMU.	Gabe Black
2010-06-02	ARM: Implement a function to decode CP15 registers to MiscReg indices.	Gabe Black