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path: root/src/arch/arm/miscregs.cc
AgeCommit message (Expand)Author
2014-10-29arm: Mark some miscregs (timer counter) registers at unverifiable.Ali Saidi
2014-09-02arm: Don't speculatively access most miscregisters.Akash Bagdia
2014-10-01arm: Use MiscRegIndex rather than int when flatteningAndreas Hansson
2014-08-13arm: change MISCREG_L2ERRSR to warn not failDam Sunwoo
2014-05-09arm: Panics in miscreg read functions can be tripped by O3 modelGeoffrey Blake
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Move Miscreg functions out of isa.hhAli Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Convert the CP15 registers from MPU to MMU.Gabe Black
2010-06-02ARM: Implement a function to decode CP15 registers to MiscReg indices.Gabe Black