| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2011-05-13 | ARM: Further break up condition code into NZ, C, V bits. | Ali Saidi | |
| Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. | |||
| 2011-05-13 | ARM: Remove the saturating (Q) condition code from the renamed register. | Ali Saidi | |
| Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit. | |||
| 2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi | |
| This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. | |||
| 2011-05-13 | ARM: Better RealView/Versatile EB platform support. | Chander Sudanthi | |
| Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively. | |||
| 2011-05-04 | ARM: Add support for MP misc regs and broadcast flushes. | Ali Saidi | |
| 2011-04-04 | ARM: Use CPU local lock before sending load to mem system. | Ali Saidi | |
| This change uses the locked_mem.hh header to handle implementing CLREX. It simplifies the current implementation greatly. | |||
| 2011-04-04 | ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works. | Ali Saidi | |
| This change fixes a small bug in the arm copyRegs() code where some registers wouldn't be copied if the processor was in a mode other than MODE_USER. Additionally, this change simplifies the way the O3 switchCpu code works by utilizing TheISA::copyRegs() to copy the required context information rather than the adhoc copying that goes on in the CPU model. The current code makes assumptions about the visibility of int and float registers that aren't true for all architectures in FS mode. | |||
| 2011-04-04 | ARM: Cleanup and small fixes to some NEON ops to match the spec. | William Wang | |
| Only certain bits of the cpacr can be written, some must be equal. Mult instructions that write the same register should do something sane | |||
| 2011-04-04 | ARM: Cleanup implementation of ITSTATE and put important code in PCState. | Ali Saidi | |
| Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects. | |||
| 2011-03-25 | Arm: Add in a missing miscRegName. | Gabe Black | |
| 2011-03-17 | ARM: Implement the Instruction Set Attribute Registers (ISAR). | Ali Saidi | |
| The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values | |||
| 2011-02-23 | ARM: Adds dummy support for a L2 latency miscreg. | Ali Saidi | |
| 2010-12-07 | O3: Make all instructions that write a misc. register not perform the write ↵ | Giacomo Gabrielli | |
| until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM). | |||
| 2010-11-15 | ARM: Add comment about the organization of the IT state register | Ali Saidi | |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black | |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP ↵ | Gabe Black | |
| access is disabled. | |||
| 2010-08-23 | ARM: Implement some more misc registers | Ali Saidi | |
| 2010-06-02 | ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, ↵ | Dam Sunwoo | |
| V2PCWUR, V2PCWUW,...) | |||
| 2010-06-02 | ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. | Gabe Black | |
| 2010-06-02 | ARM: Some TLB bug fixes. | Ali Saidi | |
| 2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi | |
| 2010-06-02 | ARM: Implement ARM CPU interrupts | Ali Saidi | |
| 2010-06-02 | ARM: Make MPIDR return 0 and ignore writes. | Gabe Black | |
| 2010-06-02 | ARM: Set the value of the MVFR0 and MVFR1 registers. | Gabe Black | |
| 2010-06-02 | ARM: Add support for VFP vector mode. | Gabe Black | |
| 2010-06-02 | ARM: Implement and update the DFSR and IFSR registers on faults. | Gabe Black | |
| 2010-06-02 | ARM: Add in some missing SCTLR fields. | Gabe Black | |
| 2010-06-02 | ARM: Warn/ignore when TLB maintenance operations are performed. | Gabe Black | |
| 2010-06-02 | ARM: Handle accesses to TLBTR. | Gabe Black | |
| 2010-06-02 | ARM: Handle accesses to the DACR. | Gabe Black | |
| 2010-06-02 | ARM: Handle accesses to TTBR0 and TTBR1. | Gabe Black | |
| 2010-06-02 | ARM: Convert the CP15 registers from MPU to MMU. | Gabe Black | |
| 2010-06-02 | ARM: Add some support for wfi/wfe/yield/etc | Ali Saidi | |
| 2010-06-02 | ARM: Move PC mode bits around so they can be used for exectrace | Ali Saidi | |
| 2010-06-02 | ARM: Update the set of FP related miscregs. | Gabe Black | |
| 2010-06-02 | ARM: Ignore attempts to disable coprocessors that aren't implemented anyway. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers. | Gabe Black | |
| 2010-06-02 | ARM: Allow access to the RGNR register. | Gabe Black | |
| 2010-06-02 | ARM: Make the MPUIR register report that 1 unified data region is supported. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn when CSSELR or CCSIDR are accessed. | Gabe Black | |
| These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert. | |||
| 2010-06-02 | ARM: Ignore/warn access to the bpimva registers. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to the dccmvac register. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to icimvau. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on iciallu. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on ICIALLUIS. | Gabe Black | |
| 2010-06-02 | ARM: Add support for the clidr register. | Gabe Black | |
| This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy. | |||
| 2010-06-02 | ARM: Decode the unimplemented data barrier CP15 accesses. | Gabe Black | |
| These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier). | |||
| 2010-06-02 | ARM: Implement a stub of CPACR. | Gabe Black | |
| This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has. | |||
| 2010-06-02 | ARM: Decode the unimplemented cp15 instruction barrier. | Gabe Black | |
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