gem5 - gem5

Age	Commit message (Collapse)	Author
2010-06-02	ARM: Implement and update the DFSR and IFSR registers on faults.	Gabe Black

2010-06-02	ARM: Add in some missing SCTLR fields.	Gabe Black

2010-06-02	ARM: Warn/ignore when TLB maintenance operations are performed.	Gabe Black

2010-06-02	ARM: Handle accesses to TLBTR.	Gabe Black

2010-06-02	ARM: Handle accesses to the DACR.	Gabe Black

2010-06-02	ARM: Handle accesses to TTBR0 and TTBR1.	Gabe Black

2010-06-02	ARM: Convert the CP15 registers from MPU to MMU.	Gabe Black

2010-06-02	ARM: Add some support for wfi/wfe/yield/etc	Ali Saidi

2010-06-02	ARM: Move PC mode bits around so they can be used for exectrace	Ali Saidi

2010-06-02	ARM: Update the set of FP related miscregs.	Gabe Black

2010-06-02	ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.	Gabe Black

2010-06-02	ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.	Gabe Black

2010-06-02	ARM: Allow access to the RGNR register.	Gabe Black

2010-06-02	ARM: Make the MPUIR register report that 1 unified data region is supported.	Gabe Black

2010-06-02	ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.	Gabe Black

2010-06-02	ARM: Ignore/warn when CSSELR or CCSIDR are accessed.	Gabe Black
	These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert.
2010-06-02	ARM: Ignore/warn access to the bpimva registers.	Gabe Black

2010-06-02	ARM: Ignore/warn on accesses to the dccmvac register.	Gabe Black

2010-06-02	ARM: Ignore/warn on accesses to icimvau.	Gabe Black

2010-06-02	ARM: Ignore/warn on iciallu.	Gabe Black

2010-06-02	ARM: Ignore/warn on ICIALLUIS.	Gabe Black

2010-06-02	ARM: Add support for the clidr register.	Gabe Black
	This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy.
2010-06-02	ARM: Decode the unimplemented data barrier CP15 accesses.	Gabe Black
	These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).
2010-06-02	ARM: Implement a stub of CPACR.	Gabe Black
	This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has.
2010-06-02	ARM: Decode the unimplemented cp15 instruction barrier.	Gabe Black

2010-06-02	ARM: Ignore accesses to DCCIMVAC.	Gabe Black

2010-06-02	ARM: Allow accesses to the software thread id registers.	Gabe Black

2010-06-02	ARM: Allow accesses to the contextidr register.	Gabe Black

2010-06-02	ARM: Warn about and ignore accesses to DCCISW.	Gabe Black
	This register is supposed to "Clean and invalidate data or unified cache line by set/way." Since there isn't a good way to do that, we'll just ignore these and warn about it.
2010-06-02	ARM: Implement a function to decode CP15 registers to MiscReg indices.	Gabe Black

2010-06-02	ARM: Replace the "never" condition with the "unconditional" condition.	Gabe Black

2010-06-02	ARM: Track the current ISA mode using the PC.	Gabe Black

2009-11-14	ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.	Gabe Black

2009-11-10	ARM: Implement fault classes.	Gabe Black
	Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-08	ARM: Add in more bits for the mon mode.	Gabe Black

2009-07-27	ARM: Add in spots for the VFP control registers.	Gabe Black

2009-06-26	ARM: Fill out the printReg function.	Gabe Black

2009-06-21	ARM: Pull some static code out of the isa desc and create miscregs.hh.	Gabe Black