| Age | Commit message (Expand) | Author |
|---|
| 2018-07-16 | arch-arm: Introduce ARMv8.1 Virtual Timer System Registers | Giacomo Travaglini |
| 2018-07-16 | arch-arm: Introduce RAS System Registers | Giacomo Travaglini |
| 2018-06-28 | arch-arm: Fix incorrect t{0,1}sz field in TTBCR | Andreas Sandberg |
| 2018-06-14 | arch-arm: Read APSR in User Mode | Giacomo Travaglini |
| 2018-05-29 | arch-arm: Remove unusued MISCREG_A64_UNIMPL | Giacomo Travaglini |
| 2018-05-29 | arch-arm: Add E2H bit to HCR_EL2 System register | Giacomo Travaglini |
| 2018-04-19 | arch-arm: Add ARMv8.1 TTBR1_EL2 register | Giacomo Travaglini |
| 2018-02-16 | arch-arm: IMPLEMENTATION DEFINED register | Giacomo Travaglini |
| 2018-02-16 | arch-arm: Arch regs and pseudo regs distinction | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Change function name for banked miscregs | Giacomo Travaglini |
| 2017-04-03 | arm: Don't panic when checking coprocessor read/write permissions | Nikos Nikoleris |
| 2016-12-19 | arm: update AArch{64,32} register mappings | Curtis Dunham |
| 2016-08-02 | arm: add stage2 translation support | Dylan Johnson |
| 2016-06-02 | arm: Rewrite ERET to behave according to the ARMv8 ARM | Andreas Sandberg |
| 2015-05-26 | arm: implement the CONTEXTIDR_EL2 system reg. | Curtis Dunham |
| 2014-10-29 | arm: Mark some miscregs (timer counter) registers at unverifiable. | Ali Saidi |
| 2014-10-01 | arm: Use MiscRegIndex rather than int when flattening | Andreas Hansson |
| 2014-04-29 | arm: use condition code registers for ARM ISA | Curtis Dunham |
| 2014-05-27 | arm: support 16kb vm granules | Curtis Dunham |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2013-10-31 | ARM: add support for TEEHBR access | Chander Sudanthi |
| 2013-01-07 | arm: Remove the register mapping hack used when copying TCs | Andreas Sandberg |
| 2012-09-25 | arm: Use a static_assert to test that miscRegName[] is complete | Andreas Sandberg |
| 2012-07-27 | ARM: fix value of MISCREG_CTR returned by readMiscReg() | Anthony Gutierrez |
| 2012-06-05 | ARM: removed extra white space | Chander Sudanthi |
| 2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
| 2012-03-01 | ARM: Add limited CP14 support. | Matt Horsnell |
| 2011-09-13 | ARM: update TLB to set request packet ASID field | Daniel Johnson |
| 2011-09-13 | CP15 c15: enable execution with accesses to c15 registers | Chander Sudanthi |
| 2011-09-13 | ARM: Implement numcpus bits in L2CTLR register. | Daniel Johnson |
| 2011-07-15 | ARM: Add two unimplemented miscellaneous registers. | Wade Walker |
| 2011-05-13 | ARM: Further break up condition code into NZ, C, V bits. | Ali Saidi |
| 2011-05-13 | ARM: Remove the saturating (Q) condition code from the renamed register. | Ali Saidi |
| 2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi |
| 2011-05-13 | ARM: Better RealView/Versatile EB platform support. | Chander Sudanthi |
| 2011-05-04 | ARM: Add support for MP misc regs and broadcast flushes. | Ali Saidi |
| 2011-04-04 | ARM: Use CPU local lock before sending load to mem system. | Ali Saidi |
| 2011-04-04 | ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works. | Ali Saidi |
| 2011-04-04 | ARM: Cleanup and small fixes to some NEON ops to match the spec. | William Wang |
| 2011-04-04 | ARM: Cleanup implementation of ITSTATE and put important code in PCState. | Ali Saidi |
| 2011-03-25 | Arm: Add in a missing miscRegName. | Gabe Black |
| 2011-03-17 | ARM: Implement the Instruction Set Attribute Registers (ISAR). | Ali Saidi |
| 2011-02-23 | ARM: Adds dummy support for a L2 latency miscreg. | Ali Saidi |
| 2010-12-07 | O3: Make all instructions that write a misc. register not perform the write u... | Giacomo Gabrielli |
| 2010-11-15 | ARM: Add comment about the organization of the IT state register | Ali Saidi |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP access... | Gabe Black |
| 2010-08-23 | ARM: Implement some more misc registers | Ali Saidi |
| 2010-06-02 | ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC... | Dam Sunwoo |
| 2010-06-02 | ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. | Gabe Black |
