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path: root/src/arch/arm/miscregs.hh
AgeCommit message (Expand)Author
2012-07-27ARM: fix value of MISCREG_CTR returned by readMiscReg()Anthony Gutierrez
2012-06-05ARM: removed extra white spaceChander Sudanthi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-04ARM: Add support for MP misc regs and broadcast flushes.Ali Saidi
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-03-25Arm: Add in a missing miscRegName.Gabe Black
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-06-02ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...Dam Sunwoo
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Implement ARM CPU interruptsAli Saidi
2010-06-02ARM: Make MPIDR return 0 and ignore writes.Gabe Black
2010-06-02ARM: Set the value of the MVFR0 and MVFR1 registers.Gabe Black
2010-06-02ARM: Add support for VFP vector mode.Gabe Black
2010-06-02ARM: Implement and update the DFSR and IFSR registers on faults.Gabe Black
2010-06-02ARM: Add in some missing SCTLR fields.Gabe Black
2010-06-02ARM: Warn/ignore when TLB maintenance operations are performed.Gabe Black
2010-06-02ARM: Handle accesses to TLBTR.Gabe Black
2010-06-02ARM: Handle accesses to the DACR.Gabe Black
2010-06-02ARM: Handle accesses to TTBR0 and TTBR1.Gabe Black
2010-06-02ARM: Convert the CP15 registers from MPU to MMU.Gabe Black
2010-06-02ARM: Add some support for wfi/wfe/yield/etcAli Saidi
2010-06-02ARM: Move PC mode bits around so they can be used for exectraceAli Saidi
2010-06-02ARM: Update the set of FP related miscregs.Gabe Black
2010-06-02ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.Gabe Black
2010-06-02ARM: Allow access to the RGNR register.Gabe Black
2010-06-02ARM: Make the MPUIR register report that 1 unified data region is supported.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.Gabe Black
2010-06-02ARM: Ignore/warn when CSSELR or CCSIDR are accessed.Gabe Black
2010-06-02ARM: Ignore/warn access to the bpimva registers.Gabe Black