gem5 - gem5

Age	Commit message (Expand)	Author
2011-09-13	ARM: Implement numcpus bits in L2CTLR register.	Daniel Johnson
2011-07-15	ARM: Add two unimplemented miscellaneous registers.	Wade Walker
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-05-13	ARM: Better RealView/Versatile EB platform support.	Chander Sudanthi
2011-05-04	ARM: Add support for MP misc regs and broadcast flushes.	Ali Saidi
2011-04-04	ARM: Use CPU local lock before sending load to mem system.	Ali Saidi
2011-04-04	ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.	Ali Saidi
2011-04-04	ARM: Cleanup and small fixes to some NEON ops to match the spec.	William Wang
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-03-25	Arm: Add in a missing miscRegName.	Gabe Black
2011-03-17	ARM: Implement the Instruction Set Attribute Registers (ISAR).	Ali Saidi
2011-02-23	ARM: Adds dummy support for a L2 latency miscreg.	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-11-15	ARM: Add comment about the organization of the IT state register	Ali Saidi
2010-08-25	ARM: Seperate out the renamable bits in the FPSCR.	Gabe Black
2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP access...	Gabe Black
2010-08-23	ARM: Implement some more misc registers	Ali Saidi
2010-06-02	ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...	Dam Sunwoo
2010-06-02	ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.	Gabe Black
2010-06-02	ARM: Some TLB bug fixes.	Ali Saidi
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi
2010-06-02	ARM: Implement ARM CPU interrupts	Ali Saidi
2010-06-02	ARM: Make MPIDR return 0 and ignore writes.	Gabe Black
2010-06-02	ARM: Set the value of the MVFR0 and MVFR1 registers.	Gabe Black
2010-06-02	ARM: Add support for VFP vector mode.	Gabe Black
2010-06-02	ARM: Implement and update the DFSR and IFSR registers on faults.	Gabe Black
2010-06-02	ARM: Add in some missing SCTLR fields.	Gabe Black
2010-06-02	ARM: Warn/ignore when TLB maintenance operations are performed.	Gabe Black
2010-06-02	ARM: Handle accesses to TLBTR.	Gabe Black
2010-06-02	ARM: Handle accesses to the DACR.	Gabe Black
2010-06-02	ARM: Handle accesses to TTBR0 and TTBR1.	Gabe Black
2010-06-02	ARM: Convert the CP15 registers from MPU to MMU.	Gabe Black
2010-06-02	ARM: Add some support for wfi/wfe/yield/etc	Ali Saidi
2010-06-02	ARM: Move PC mode bits around so they can be used for exectrace	Ali Saidi
2010-06-02	ARM: Update the set of FP related miscregs.	Gabe Black
2010-06-02	ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.	Gabe Black
2010-06-02	ARM: Allow access to the RGNR register.	Gabe Black
2010-06-02	ARM: Make the MPUIR register report that 1 unified data region is supported.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.	Gabe Black
2010-06-02	ARM: Ignore/warn when CSSELR or CCSIDR are accessed.	Gabe Black
2010-06-02	ARM: Ignore/warn access to the bpimva registers.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to the dccmvac register.	Gabe Black
2010-06-02	ARM: Ignore/warn on accesses to icimvau.	Gabe Black
2010-06-02	ARM: Ignore/warn on iciallu.	Gabe Black
2010-06-02	ARM: Ignore/warn on ICIALLUIS.	Gabe Black
2010-06-02	ARM: Add support for the clidr register.	Gabe Black
2010-06-02	ARM: Decode the unimplemented data barrier CP15 accesses.	Gabe Black