index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
arm
/
miscregs.hh
Age
Commit message (
Collapse
)
Author
2010-06-02
ARM: Decode the unimplemented cp15 instruction barrier.
Gabe Black
2010-06-02
ARM: Ignore accesses to DCCIMVAC.
Gabe Black
2010-06-02
ARM: Allow accesses to the software thread id registers.
Gabe Black
2010-06-02
ARM: Allow accesses to the contextidr register.
Gabe Black
2010-06-02
ARM: Warn about and ignore accesses to DCCISW.
Gabe Black
This register is supposed to "Clean and invalidate data or unified cache line by set/way." Since there isn't a good way to do that, we'll just ignore these and warn about it.
2010-06-02
ARM: Implement a function to decode CP15 registers to MiscReg indices.
Gabe Black
2010-06-02
ARM: Replace the "never" condition with the "unconditional" condition.
Gabe Black
2010-06-02
ARM: Track the current ISA mode using the PC.
Gabe Black
2009-11-14
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
Gabe Black
2009-11-10
ARM: Implement fault classes.
Gabe Black
Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-08
ARM: Add in more bits for the mon mode.
Gabe Black
2009-07-27
ARM: Add in spots for the VFP control registers.
Gabe Black
2009-06-26
ARM: Fill out the printReg function.
Gabe Black
2009-06-21
ARM: Pull some static code out of the isa desc and create miscregs.hh.
Gabe Black