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These registers provide information about the caches. Since we can't provide
that information, these will be harmlessly inert.
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This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
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These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory
Barrier).
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This register controls access to the coprocessors. This doesn't actually
implement it, it allows writes which don't turn anything off. In other words,
it allows the simulated program to ask for what it already has.
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This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
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Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
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