| Age | Commit message (Expand) | Author |
|---|
| 2010-06-02 | ARM: Decode the unimplemented data barrier CP15 accesses. | Gabe Black |
| 2010-06-02 | ARM: Implement a stub of CPACR. | Gabe Black |
| 2010-06-02 | ARM: Decode the unimplemented cp15 instruction barrier. | Gabe Black |
| 2010-06-02 | ARM: Ignore accesses to DCCIMVAC. | Gabe Black |
| 2010-06-02 | ARM: Allow accesses to the software thread id registers. | Gabe Black |
| 2010-06-02 | ARM: Allow accesses to the contextidr register. | Gabe Black |
| 2010-06-02 | ARM: Warn about and ignore accesses to DCCISW. | Gabe Black |
| 2010-06-02 | ARM: Implement a function to decode CP15 registers to MiscReg indices. | Gabe Black |
| 2010-06-02 | ARM: Replace the "never" condition with the "unconditional" condition. | Gabe Black |
| 2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black |
| 2009-11-14 | ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. | Gabe Black |
| 2009-11-10 | ARM: Implement fault classes. | Gabe Black |
| 2009-11-08 | ARM: Add in more bits for the mon mode. | Gabe Black |
| 2009-07-27 | ARM: Add in spots for the VFP control registers. | Gabe Black |
| 2009-06-26 | ARM: Fill out the printReg function. | Gabe Black |
| 2009-06-21 | ARM: Pull some static code out of the isa desc and create miscregs.hh. | Gabe Black |
