gem5 - gem5

Age	Commit message (Expand)	Author
2019-04-11	arch-arm: Enable PMSELR_EL0 read in PMU	Giacomo Travaglini
2019-02-08	arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30	Giacomo Travaglini
2019-02-08	arch-arm: Allow ArmPPI usage for PMU	Giacomo Travaglini
2019-02-08	arch-arm: Fix initialization of PMU counters	Ruben Ayrapetyan
2019-01-22	arm: Get rid of some register type definitions.	Gabe Black
2018-09-28	arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET	Giacomo Travaglini
2018-09-10	dev-arm: Factory SimObject for generating ArmInterruptPin	Giacomo Travaglini
2018-09-10	arm: Use the interrupt adaptor in the PMU	Andreas Sandberg
2017-11-21	arch-arm: ArmPMU refactor	Jose Marinho
2017-11-20	arch-arm: Ensure counters keep events on checkpoint resume	Jose Marinho
2017-08-30	arch-arm: Only increment SW PMU counters on writes to PMSWINC	Jose Marinho
2017-07-10	arch-arm: Support PMU evens in the 0x4000-0x4040 range	Jose Marinho
2017-05-24	arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU	Andreas Sandberg
2016-04-15	arm,dev: remove PMU assertion hit on reset	Bjoern A. Zeeb
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2014-12-23	arm: Add support for filtering in the PMU	Andreas Sandberg
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-10-16	arm: Add a model of an ARM PMUv3	Andreas Sandberg