gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2014-04-29	arm: use condition code registers for ARM ISA	Curtis Dunham
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-04-23	ISA: Put parser generated files in a "generated" directory.	Gabe Black
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2010-08-25	ARM: Limited implementation of dprintk.	Ali Saidi
2010-08-25	ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)	Min Kyu Jeong
2010-08-25	ARM: Eliminate some unused enums.	Gabe Black
2010-08-23	ARM: Add some registers for big loads/stores to support neon.	Ali Saidi
2010-07-13	ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.	Gabe Black
2010-06-02	ARM: Allow flattening into any mode.	Gabe Black
2010-06-02	ARM: Fix the constant describing the number of floating point registers.	Gabe Black
2009-11-08	ARM: Get rid of NumInternalProcRegs.	Gabe Black
2009-11-08	ARM: Set up an intregs.hh for ARM.	Gabe Black
2009-11-07	ARM: Get rid of some unneeded register indexes.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black