gem5 - gem5

Age	Commit message (Expand)	Author
2018-02-07	arch-arm: Change function name for banked miscregs	Giacomo Travaglini
2017-12-22	arch,cpu: "virtualize" the TLB interface.	Gabe Black
2017-12-14	misc: Updates for gcc7.2 for x86	Jason Lowe-Power
2017-06-20	arm: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2017-04-03	arm: Treat Write-Through Normal memory as Non-Cacheable	Nikos Nikoleris
2016-08-02	arm: refactor page table walking	Curtis Dunham
2016-08-02	arm: Fix stage 2 memory attribute checking in AArch64	Dylan Johnson
2016-08-02	arm: Fix stage 2 determination in table walker	Dylan Johnson
2016-08-02	arm: Refactor aarch64 table walk logic to remove redundancy	Dylan Johnson
2016-08-02	arm: add stage2 translation support	Dylan Johnson
2016-08-02	arm: enable EL2 support	Curtis Dunham
2016-06-06	sim: Call regStats of base-class as well	Stephan Diestelhorst
2016-06-02	arm: refactor page table format determination	Curtis Dunham
2016-03-21	arm: Refactor the TLB test interface	Andreas Sandberg
2015-10-29	arm: Add secure flag to TableWalker request when needed	Nathanael Premillieu
2015-07-07	sim: Refactor and simplify the drain API	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-06-21	arm: Cleanup arch headers to remove dma_device.hh dependency	Andreas Sandberg
2015-05-15	arm: Identify table-walker requests	Andreas Hansson
2015-03-02	arm: Share a port for the two table walker objects	Andreas Hansson
2014-12-23	arm: Add stats to table walker	Curtis Dunham
2014-12-02	arm: Fix TLB ignoring faults when table walking	Andrew Bardsley
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-10-29	arm, mem: Fix drain bug and provide drain prints for more components.	Ali Saidi
2014-10-16	arch: Use shared_ptr for all Faults	Andreas Hansson
2014-10-01	arm: Use MiscRegIndex rather than int when flattening	Andreas Hansson
2014-09-12	style: Fix line continuation, especially in debug messages	Andrew Bardsley
2014-05-27	arm: support 16kb vm granules	Curtis Dunham
2014-03-07	arm: Handle functional TLB walks properly	Geoffrey Blake
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2013-02-15	arm: fix a page table walker issue where a page could be translated multiple ...	Mrinmoy Ghosh
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-01-07	arm: Fix draining of the pagetable walker when squashing	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-25	arm: Use table walker clock that is inherited from CPU	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-05-23	MEM: Add a snooping DMA port subclass for table walker	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2011-12-01	Device: Make changes necessary to support a coherent page walker cache.	Mitchell Hayenga
2011-08-19	ARM: Fix a memory leak with the table walker.	Ali Saidi