Age | Commit message (Collapse) | Author | |
---|---|---|---|
2011-04-15 | includes: sort all includes | Nathan Binkert | |
2011-02-11 | O3: Fix a few bugs in the TableWalker object. | Giacomo Gabrielli | |
Uncacheable requests were set as such only in atomic mode. currState->delayed is checked in place of currState->timing for resetting currState in atomic mode. | |||
2011-02-03 | Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh. | Gabe Black | |
--HG-- rename : src/sim/fault.hh => src/sim/fault_fwd.hh | |||
2010-11-15 | ARM: Add support for switching CPUs | Ali Saidi | |
2010-11-08 | ARM: Add checkpointing support | Ali Saidi | |
2010-11-08 | ARM: Don't return the result of a table walk the same cycle it's completed. | Ali Saidi | |
The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once. | |||
2010-10-01 | ARM: Implement functional virtual to physical address translation | Ali Saidi | |
for debugging and program introspection. | |||
2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black | |
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. | |||
2010-08-25 | ARM: Seperate the queues of L1 and L2 walker states. | Gene WU | |
2010-08-23 | ARM: Fix Uncachable TLB requests and decoding of xn bit | Gene Wu | |
2010-08-23 | ARM: Use a stl queue for the table walker state | Dam Sunwoo | |
2010-06-02 | ARM: Allow multiple outstanding TLB walks to queue. | Dam Sunwoo | |
2010-06-02 | ARM TLB: Fix bug in memAttrs getting a bogus thread context | Ali Saidi | |
2010-06-02 | ARM: Support table walks in timing mode. | Dam Sunwoo | |
2010-06-02 | ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, ↵ | Dam Sunwoo | |
V2PCWUR, V2PCWUW,...) | |||
2010-06-02 | ARM: Some TLB bug fixes. | Ali Saidi | |
2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi | |