gem5 - gem5

Age	Commit message (Expand)	Author
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2011-04-15	includes: sort all includes	Nathan Binkert
2011-02-11	O3: Fix a few bugs in the TableWalker object.	Giacomo Gabrielli
2011-02-03	Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.	Gabe Black
2010-11-15	ARM: Add support for switching CPUs	Ali Saidi
2010-11-08	ARM: Add checkpointing support	Ali Saidi
2010-11-08	ARM: Don't return the result of a table walk the same cycle it's completed.	Ali Saidi
2010-10-01	ARM: Implement functional virtual to physical address translation	Ali Saidi
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-08-25	ARM: Seperate the queues of L1 and L2 walker states.	Gene WU
2010-08-23	ARM: Fix Uncachable TLB requests and decoding of xn bit	Gene Wu
2010-08-23	ARM: Use a stl queue for the table walker state	Dam Sunwoo
2010-06-02	ARM: Allow multiple outstanding TLB walks to queue.	Dam Sunwoo
2010-06-02	ARM TLB: Fix bug in memAttrs getting a bogus thread context	Ali Saidi
2010-06-02	ARM: Support table walks in timing mode.	Dam Sunwoo
2010-06-02	ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...	Dam Sunwoo
2010-06-02	ARM: Some TLB bug fixes.	Ali Saidi
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi