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path: root/src/arch/arm/table_walker.hh
AgeCommit message (Expand)Author
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-05-23DMA: Split the DMA device and IO device into seperate filesAndreas Hansson
2012-05-23MEM: Add a snooping DMA port subclass for table walkerAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2011-04-15includes: sort all includesNathan Binkert
2011-02-11O3: Fix a few bugs in the TableWalker object.Giacomo Gabrielli
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2010-11-15ARM: Add support for switching CPUsAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-11-08ARM: Don't return the result of a table walk the same cycle it's completed.Ali Saidi
2010-10-01ARM: Implement functional virtual to physical address translationAli Saidi
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-25ARM: Seperate the queues of L1 and L2 walker states.Gene WU
2010-08-23ARM: Fix Uncachable TLB requests and decoding of xn bitGene Wu
2010-08-23ARM: Use a stl queue for the table walker stateDam Sunwoo
2010-06-02ARM: Allow multiple outstanding TLB walks to queue.Dam Sunwoo
2010-06-02ARM TLB: Fix bug in memAttrs getting a bogus thread contextAli Saidi
2010-06-02ARM: Support table walks in timing mode.Dam Sunwoo
2010-06-02ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...Dam Sunwoo
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi