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path: root/src/arch/arm/tlb.cc
AgeCommit message (Expand)Author
2014-09-12style: Fix line continuation, especially in debug messagesAndrew Bardsley
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
2013-06-03arch: Create a method to finalize physical addressesAndreas Sandberg
2013-02-15arm: fix a page table walker issue where a page could be translated multiple ...Mrinmoy Ghosh
2013-01-07arm: Invalidate cached TLB configuration in drainResumeAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-29Implement Ali's review feedback.Gabe Black
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-16ARM: Turn on the page table walker on ARM in SE mode.Gabe Black
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-08-19ARM: Mark some variables uncacheable until boot all CPUs are enabled.Ali Saidi
2011-06-16ARM: Handle case where new TLB size is different from previous TLB size.Ali Saidi
2011-06-16ARM: Fix memset on TLB flush and initializationChander Sudanthi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-04ARM: Fix table walk going on while ASID changes errorAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-01-18O3: Fixes the way prefetches are handled inside the iew unit.Matt Horsnell
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-11-15ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.Ali Saidi
2010-11-08ARM: Add some TLB statistics for ARMAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
2010-10-01ARM: Make the TLB a little bit faster by moving most recently used items to f...Ali Saidi
2010-10-01ARM: Implement functional virtual to physical address translationAli Saidi
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches whe...Gene Wu
2010-08-23ARM: Make sure that software prefetch instructions can't change the state of ...Gene Wu
2010-08-23ARM: Fix Uncachable TLB requests and decoding of xn bitGene Wu
2010-08-23ARM: For non-cachable accesses set the UNCACHABLE flagGene Wu
2010-08-23ARM: Implement CLREXGene Wu
2010-06-15stats: only consider a formula initialized if there is a formulaNathan Binkert
2010-06-02ARM: Allow multiple outstanding TLB walks to queue.Dam Sunwoo
2010-06-02ARM TLB: Fix bug in memAttrs getting a bogus thread contextAli Saidi
2010-06-02ARM: Support table walks in timing mode.Dam Sunwoo
2010-06-02ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...Dam Sunwoo
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Start over with translation from Alpha code as opposed to something that...Ali Saidi
2010-06-02ARM: Implement and update the DFSR and IFSR registers on faults.Gabe Black
2010-06-02ARM: Warn about not implementing MPU translation, not panic about MMU.Gabe Black
2010-06-02ARM: Implement the V7 version of alignment checking.Gabe Black
2010-06-02ARM: Track the current ISA mode using the PC.Gabe Black
2009-11-17ARM: Boilerplate full-system code.Ali Saidi