Age | Commit message (Collapse) | Author | |
---|---|---|---|
2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang | |
This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again. | |||
2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black | |
2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake | |
Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification. | |||
2012-01-29 | Implement Ali's review feedback. | Gabe Black | |
Try to decrease indentation, and remove some redundant FullSystem checks. | |||
2011-11-02 | SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. | Gabe Black | |
2011-10-16 | ARM: Turn on the page table walker on ARM in SE mode. | Gabe Black | |
2011-09-13 | ARM: update TLB to set request packet ASID field | Daniel Johnson | |
2011-08-19 | ARM: Mark some variables uncacheable until boot all CPUs are enabled. | Ali Saidi | |
There are a set of locations is the linux kernel that are managed via cache maintence instructions until all processors enable their MMUs & TLBs. Writes to these locations are manually flushed from the cache to main memory when the occur so that cores operating without their MMU enabled and only issuing uncached accesses can receive the correct data. Unfortuantely, gem5 doesn't support any kind of software directed maintence of the cache. Until such time as that support exists this patch marks the specific cache blocks that need to be coherent as non-cacheable until all CPUs enable their MMU and thus allows gem5 to boot MP systems with caches enabled (a requirement for booting an O3 cpu and thus an O3 CPU regression). | |||
2011-06-16 | ARM: Handle case where new TLB size is different from previous TLB size. | Ali Saidi | |
After a checkpoint we need to make sure that we restore the right number of entries. | |||
2011-06-16 | ARM: Fix memset on TLB flush and initialization | Chander Sudanthi | |
Instead of clearing the entire TLB on initialization and flush, the code was clearing only one element. This patch corrects the memsets in the init and flush routines. | |||
2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert | |
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help | |||
2011-04-04 | ARM: Fix table walk going on while ASID changes error | Ali Saidi | |
2011-02-23 | ARM: Fix bug that let two table walks occur in parallel. | Ali Saidi | |
2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli | |
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution. | |||
2011-01-18 | O3: Fixes the way prefetches are handled inside the iew unit. | Matt Horsnell | |
This patch prevents the prefetch being added to the instCommit queue twice. | |||
2010-12-07 | ARM: Support switchover with hardware table walkers | Ali Saidi | |
2010-11-15 | ARM: Cache the misc regs at the TLB to limit readMiscReg() calls. | Ali Saidi | |
2010-11-08 | ARM: Add some TLB statistics for ARM | Ali Saidi | |
2010-11-08 | ARM: Add checkpointing support | Ali Saidi | |
2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black | |
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. | |||
2010-10-13 | Mem: Change the CLREX flag to CLEAR_LL. | Gabe Black | |
CLREX is the name of an ARM instruction, not a name for this generic flag. | |||
2010-10-01 | ARM: Make the TLB a little bit faster by moving most recently used items to ↵ | Ali Saidi | |
front of list | |||
2010-10-01 | ARM: Implement functional virtual to physical address translation | Ali Saidi | |
for debugging and program introspection. | |||
2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches ↵ | Gene Wu | |
when it in received | |||
2010-08-23 | ARM: Make sure that software prefetch instructions can't change the state of ↵ | Gene Wu | |
the TLB | |||
2010-08-23 | ARM: Fix Uncachable TLB requests and decoding of xn bit | Gene Wu | |
2010-08-23 | ARM: For non-cachable accesses set the UNCACHABLE flag | Gene Wu | |
2010-08-23 | ARM: Implement CLREX | Gene Wu | |
2010-06-15 | stats: only consider a formula initialized if there is a formula | Nathan Binkert | |
2010-06-02 | ARM: Allow multiple outstanding TLB walks to queue. | Dam Sunwoo | |
2010-06-02 | ARM TLB: Fix bug in memAttrs getting a bogus thread context | Ali Saidi | |
2010-06-02 | ARM: Support table walks in timing mode. | Dam Sunwoo | |
2010-06-02 | ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, ↵ | Dam Sunwoo | |
V2PCWUR, V2PCWUW,...) | |||
2010-06-02 | ARM: Some TLB bug fixes. | Ali Saidi | |
2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi | |
2010-06-02 | ARM: Start over with translation from Alpha code as opposed to something ↵ | Ali Saidi | |
that has cruft from 4 different ISAs. | |||
2010-06-02 | ARM: Implement and update the DFSR and IFSR registers on faults. | Gabe Black | |
2010-06-02 | ARM: Warn about not implementing MPU translation, not panic about MMU. | Gabe Black | |
We'll start out with a stbu version of PMSA and switch over to VMSA for the full implementation. | |||
2010-06-02 | ARM: Implement the V7 version of alignment checking. | Gabe Black | |
2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black | |
2009-11-17 | ARM: Boilerplate full-system code. | Ali Saidi | |
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh | |||
2009-08-01 | Clean up some inconsistencies with Request flags. | Steve Reinhardt | |
2009-04-21 | arm: Unify the ARM tlb. We forgot about this when we did the rest. | Nathan Binkert | |
This code compiles, but there are no tests still | |||
2009-04-06 | Merge ARM into the head. ARM will compile but may not actually work. | Gabe Black | |
2009-04-05 | arm: add ARM support to M5 | Stephen Hines | |