| Age | Commit message (Expand) | Author |
|---|
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake |
| 2012-01-29 | Implement Ali's review feedback. | Gabe Black |
| 2011-11-02 | SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. | Gabe Black |
| 2011-10-16 | ARM: Turn on the page table walker on ARM in SE mode. | Gabe Black |
| 2011-09-13 | ARM: update TLB to set request packet ASID field | Daniel Johnson |
| 2011-08-19 | ARM: Mark some variables uncacheable until boot all CPUs are enabled. | Ali Saidi |
| 2011-06-16 | ARM: Handle case where new TLB size is different from previous TLB size. | Ali Saidi |
| 2011-06-16 | ARM: Fix memset on TLB flush and initialization | Chander Sudanthi |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
| 2011-04-04 | ARM: Fix table walk going on while ASID changes error | Ali Saidi |
| 2011-02-23 | ARM: Fix bug that let two table walks occur in parallel. | Ali Saidi |
| 2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli |
| 2011-01-18 | O3: Fixes the way prefetches are handled inside the iew unit. | Matt Horsnell |
| 2010-12-07 | ARM: Support switchover with hardware table walkers | Ali Saidi |
| 2010-11-15 | ARM: Cache the misc regs at the TLB to limit readMiscReg() calls. | Ali Saidi |
| 2010-11-08 | ARM: Add some TLB statistics for ARM | Ali Saidi |
| 2010-11-08 | ARM: Add checkpointing support | Ali Saidi |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-10-13 | Mem: Change the CLREX flag to CLEAR_LL. | Gabe Black |
| 2010-10-01 | ARM: Make the TLB a little bit faster by moving most recently used items to f... | Ali Saidi |
| 2010-10-01 | ARM: Implement functional virtual to physical address translation | Ali Saidi |
| 2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches whe... | Gene Wu |
| 2010-08-23 | ARM: Make sure that software prefetch instructions can't change the state of ... | Gene Wu |
| 2010-08-23 | ARM: Fix Uncachable TLB requests and decoding of xn bit | Gene Wu |
| 2010-08-23 | ARM: For non-cachable accesses set the UNCACHABLE flag | Gene Wu |
| 2010-08-23 | ARM: Implement CLREX | Gene Wu |
| 2010-06-15 | stats: only consider a formula initialized if there is a formula | Nathan Binkert |
| 2010-06-02 | ARM: Allow multiple outstanding TLB walks to queue. | Dam Sunwoo |
| 2010-06-02 | ARM TLB: Fix bug in memAttrs getting a bogus thread context | Ali Saidi |
| 2010-06-02 | ARM: Support table walks in timing mode. | Dam Sunwoo |
| 2010-06-02 | ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC... | Dam Sunwoo |
| 2010-06-02 | ARM: Some TLB bug fixes. | Ali Saidi |
| 2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi |
| 2010-06-02 | ARM: Start over with translation from Alpha code as opposed to something that... | Ali Saidi |
| 2010-06-02 | ARM: Implement and update the DFSR and IFSR registers on faults. | Gabe Black |
| 2010-06-02 | ARM: Warn about not implementing MPU translation, not panic about MMU. | Gabe Black |
| 2010-06-02 | ARM: Implement the V7 version of alignment checking. | Gabe Black |
| 2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black |
| 2009-11-17 | ARM: Boilerplate full-system code. | Ali Saidi |
| 2009-08-01 | Clean up some inconsistencies with Request flags. | Steve Reinhardt |
| 2009-04-21 | arm: Unify the ARM tlb. We forgot about this when we did the rest. | Nathan Binkert |
| 2009-04-06 | Merge ARM into the head. ARM will compile but may not actually work. | Gabe Black |
| 2009-04-05 | arm: add ARM support to M5 | Stephen Hines |
