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path: root/src/arch/arm/tlb.cc
AgeCommit message (Expand)Author
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-06-02arm: refactor page table format determinationCurtis Dunham
2016-05-31arm: Correctly check translation mode (aarch64/aarch32)Andreas Sandberg
2016-05-26arm: Fix incorrect TLB permission check in aarch32Andreas Sandberg
2016-03-21arm: Refactor the TLB test interfaceAndreas Sandberg
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-09-30arm: Change TLB Software CachingMitch Hayenga
2015-08-21arm, mem: Remove unused CLEAR_LL request flagAndreas Hansson
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-06-21arm: Cleanup arch headers to remove dma_device.hh dependencyAndreas Sandberg
2015-05-26arm: Make address translation faster with better cachingNathanael Premillieu
2015-05-05arm: Relax ordering for some uncacheable accessesAndreas Sandberg
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-05-05arm: Remove unnecessary boot uncachabilityAndreas Hansson
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
2014-12-23arm: Raise an alignment fault if a PC has illegal alignmentAndreas Sandberg
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-10-29arm: Fix multi-system AArch64 boot w/caches.Ali Saidi
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-10-16arm: Add TLB PMU probesAndreas Sandberg
2014-09-27arm: Fixed undefined behaviours identified by gccAndreas Hansson
2014-09-12style: Fix line continuation, especially in debug messagesAndrew Bardsley
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
2013-06-03arch: Create a method to finalize physical addressesAndreas Sandberg
2013-02-15arm: fix a page table walker issue where a page could be translated multiple ...Mrinmoy Ghosh
2013-01-07arm: Invalidate cached TLB configuration in drainResumeAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-29Implement Ali's review feedback.Gabe Black
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-16ARM: Turn on the page table walker on ARM in SE mode.Gabe Black
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-08-19ARM: Mark some variables uncacheable until boot all CPUs are enabled.Ali Saidi
2011-06-16ARM: Handle case where new TLB size is different from previous TLB size.Ali Saidi
2011-06-16ARM: Fix memset on TLB flush and initializationChander Sudanthi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-04ARM: Fix table walk going on while ASID changes errorAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
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