gem5 - gem5

Age	Commit message (Expand)	Author
2017-02-21	arm: Blame the right instruction address on a Prefetch Abort	Nikos Nikoleris
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-08-15	cpu, arch: fix the type used for the request flags	Nikos Nikoleris
2016-08-02	arm: Add TLBI instruction for stage 2 IPA's	Dylan Johnson
2016-08-02	arm: Fix stage 2 determination in table walker	Dylan Johnson
2016-08-02	arm: Fix EL perceived at TLB for address translation instructions	Dylan Johnson
2016-08-02	arm: add stage2 translation support	Dylan Johnson
2016-07-11	arm: Don't consult the TLB test iface for functional translations	Andreas Sandberg
2016-06-06	sim: Call regStats of base-class as well	Stephan Diestelhorst
2016-06-02	arm: refactor page table format determination	Curtis Dunham
2016-05-31	arm: Correctly check translation mode (aarch64/aarch32)	Andreas Sandberg
2016-05-26	arm: Fix incorrect TLB permission check in aarch32	Andreas Sandberg
2016-03-21	arm: Refactor the TLB test interface	Andreas Sandberg
2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
2015-09-30	arm: Change TLB Software Caching	Mitch Hayenga
2015-08-21	arm, mem: Remove unused CLEAR_LL request flag	Andreas Hansson
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-06-21	arm: Cleanup arch headers to remove dma_device.hh dependency	Andreas Sandberg
2015-05-26	arm: Make address translation faster with better caching	Nathanael Premillieu
2015-05-05	arm: Relax ordering for some uncacheable accesses	Andreas Sandberg
2015-05-05	mem, cpu: Add a separate flag for strictly ordered memory	Andreas Sandberg
2015-05-05	arm: Remove unnecessary boot uncachability	Andreas Hansson
2015-03-02	arm: Share a port for the two table walker objects	Andreas Hansson
2014-12-23	arm: Raise an alignment fault if a PC has illegal alignment	Andreas Sandberg
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-10-29	arm: Fix multi-system AArch64 boot w/caches.	Ali Saidi
2014-10-16	arch: Use shared_ptr for all Faults	Andreas Hansson
2014-10-16	arm: Add TLB PMU probes	Andreas Sandberg
2014-09-27	arm: Fixed undefined behaviours identified by gcc	Andreas Hansson
2014-09-12	style: Fix line continuation, especially in debug messages	Andrew Bardsley
2014-05-09	arch, arm: Preserve TLB bootUncacheability when switching CPUs	Geoffrey Blake
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2013-10-31	mem: Add privilege info to request class	Prakash Ramrakhyani
2013-06-03	arch: Create a method to finalize physical addresses	Andreas Sandberg
2013-02-15	arm: fix a page table walker issue where a page could be translated multiple ...	Mrinmoy Ghosh
2013-01-07	arm: Invalidate cached TLB configuration in drainResume	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-29	Implement Ali's review feedback.	Gabe Black
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.	Gabe Black
2011-10-16	ARM: Turn on the page table walker on ARM in SE mode.	Gabe Black
2011-09-13	ARM: update TLB to set request packet ASID field	Daniel Johnson
2011-08-19	ARM: Mark some variables uncacheable until boot all CPUs are enabled.	Ali Saidi
2011-06-16	ARM: Handle case where new TLB size is different from previous TLB size.	Ali Saidi
2011-06-16	ARM: Fix memset on TLB flush and initialization	Chander Sudanthi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-04	ARM: Fix table walk going on while ASID changes error	Ali Saidi