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path: root/src/arch/arm/tlb.cc
AgeCommit message (Expand)Author
2019-09-18arch-arm: Fix Data Abort ISS when caused by Atomic operationGiacomo Travaglini
2019-09-18arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1Giacomo Travaglini
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
2019-08-05arch-arm: Implement ARMv8.1-PAN, Privileged access neverGiacomo Travaglini
2019-07-17arch-arm: Use ExceptionLevel type in TlbEntryGiacomo Travaglini
2019-06-26arch, arm: Update miscRegs in getTEAnouk Van Laer
2019-05-14arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcherJavier Bueno
2019-04-26arch-arm: updateMiscReg not setting isHyp in aarch64Giacomo Travaglini
2019-04-25arch-arm: Remove un-needed hyp flag in TLBI operationsGiacomo Travaglini
2019-03-21dev-arm: ambiguous use of getPort()Andrea Mondelli
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
2018-11-05arch, arm: Effect of AT instructions on descriptor handlingAnouk Van Laer
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
2018-02-16arch-arm: Fix syntax error in TLB::getResultTeChuan Zhu
2018-02-07arch-arm: Check cache maintenance insts for permission faultsNikos Nikoleris
2018-02-07arch-arm: Change function name for banked miscregsGiacomo Travaglini
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-05arm: Add CMO support for Non-Cacheable memoryNikos Nikoleris
2017-05-09arm: Add support for memory-mapped m5opsAndreas Sandberg
2017-02-21arm: Blame the right instruction address on a Prefetch AbortNikos Nikoleris
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-06-02arm: refactor page table format determinationCurtis Dunham
2016-05-31arm: Correctly check translation mode (aarch64/aarch32)Andreas Sandberg
2016-05-26arm: Fix incorrect TLB permission check in aarch32Andreas Sandberg
2016-03-21arm: Refactor the TLB test interfaceAndreas Sandberg
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-09-30arm: Change TLB Software CachingMitch Hayenga
2015-08-21arm, mem: Remove unused CLEAR_LL request flagAndreas Hansson
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-06-21arm: Cleanup arch headers to remove dma_device.hh dependencyAndreas Sandberg
2015-05-26arm: Make address translation faster with better cachingNathanael Premillieu
2015-05-05arm: Relax ordering for some uncacheable accessesAndreas Sandberg
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-05-05arm: Remove unnecessary boot uncachabilityAndreas Hansson
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
2014-12-23arm: Raise an alignment fault if a PC has illegal alignmentAndreas Sandberg
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-10-29arm: Fix multi-system AArch64 boot w/caches.Ali Saidi
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson