| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black | |
| 2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake | |
| Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification. | |||
| 2011-10-16 | ARM: Turn on the page table walker on ARM in SE mode. | Gabe Black | |
| 2011-09-13 | ARM: update TLB to set request packet ASID field | Daniel Johnson | |
| 2011-08-19 | ARM: Mark some variables uncacheable until boot all CPUs are enabled. | Ali Saidi | |
| There are a set of locations is the linux kernel that are managed via cache maintence instructions until all processors enable their MMUs & TLBs. Writes to these locations are manually flushed from the cache to main memory when the occur so that cores operating without their MMU enabled and only issuing uncached accesses can receive the correct data. Unfortuantely, gem5 doesn't support any kind of software directed maintence of the cache. Until such time as that support exists this patch marks the specific cache blocks that need to be coherent as non-cacheable until all CPUs enable their MMU and thus allows gem5 to boot MP systems with caches enabled (a requirement for booting an O3 cpu and thus an O3 CPU regression). | |||
| 2011-05-13 | ARM: Better RealView/Versatile EB platform support. | Chander Sudanthi | |
| Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively. | |||
| 2011-04-15 | includes: sort all includes | Nathan Binkert | |
| 2011-02-03 | Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh. | Gabe Black | |
| --HG-- rename : src/sim/fault.hh => src/sim/fault_fwd.hh | |||
| 2011-01-03 | Make commenting on close namespace brackets consistent. | Steve Reinhardt | |
| Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. | |||
| 2010-12-20 | Style: Replace some tabs with spaces. | Gabe Black | |
| 2010-12-07 | ARM: Support switchover with hardware table walkers | Ali Saidi | |
| 2010-11-15 | ARM: Cache the misc regs at the TLB to limit readMiscReg() calls. | Ali Saidi | |
| 2010-11-08 | ARM: Add some TLB statistics for ARM | Ali Saidi | |
| 2010-11-08 | ARM: Add checkpointing support | Ali Saidi | |
| 2010-10-01 | ARM: Make the TLB a little bit faster by moving most recently used items to ↵ | Ali Saidi | |
| front of list | |||
| 2010-10-01 | ARM: Implement functional virtual to physical address translation | Ali Saidi | |
| for debugging and program introspection. | |||
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black | |
| Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. | |||
| 2010-08-25 | ARM: Implement all ARM SIMD instructions. | Gabe Black | |
| 2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches ↵ | Gene Wu | |
| when it in received | |||
| 2010-08-23 | ARM: Implement CLREX | Gene Wu | |
| 2010-06-15 | stats: only consider a formula initialized if there is a formula | Nathan Binkert | |
| 2010-06-02 | ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, ↵ | Dam Sunwoo | |
| V2PCWUR, V2PCWUW,...) | |||
| 2010-06-02 | ARM: Some TLB bug fixes. | Ali Saidi | |
| 2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi | |
| 2010-06-02 | ARM: Start over with translation from Alpha code as opposed to something ↵ | Ali Saidi | |
| that has cruft from 4 different ISAs. | |||
| 2010-06-02 | ARM: Implement the V7 version of alignment checking. | Gabe Black | |
| 2009-04-21 | arm: Unify the ARM tlb. We forgot about this when we did the rest. | Nathan Binkert | |
| This code compiles, but there are no tests still | |||
| 2009-04-06 | Merge ARM into the head. ARM will compile but may not actually work. | Gabe Black | |
| 2009-04-05 | arm: add ARM support to M5 | Stephen Hines | |
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