gem5 - gem5

Age	Commit message (Expand)	Author
2019-11-26	arch-arm: Make the Tarmac parsed registers case insensitive	Giacomo Travaglini
2019-11-18	arch-arm: R/W interface to AArch32 HCR2 misc reg	Adrian Herrera
2019-11-11	arch-arm: Fix TarmacParser handling of 64bit LD/ST	Giacomo Travaglini
2019-11-11	arch-arm: Provide SVE support to the TarmacTracer	Giacomo Travaglini
2019-11-11	arch-arm: Provide SVE support to the TarmacParser	Giacomo Gabrielli
2019-04-30	arch: Stop using TheISA within the ISAs.	Gabe Black
2019-02-12	python: Don't assume SimObjects live in the global namespace	Andreas Sandberg
2019-01-31	arch: cpu: Rename FloatRegBits to FloatReg.	Gabe Black
2018-12-20	arch, cpu: Remove float type accessors.	Gabe Black
2018-10-01	arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register	Giacomo Travaglini
2018-06-11	misc: Using smart pointers for memory Requests	Giacomo Travaglini
2018-04-06	arch-arm: Add support for Tarmac trace generation	Giacomo Travaglini
2018-04-06	arch-arm: Add support for Tarmac trace-based simulation	Giacomo Travaglini