gem5 - gem5

Age	Commit message (Collapse)	Author
2010-10-22	ISA: Simplify various implementations of completeAcc.	Gabe Black

2010-10-22	ARM: Don't pretend to writeback registers in initiateAcc.	Gabe Black

2010-10-15	GetArgument: Rework getArgument so that X86_FS compiles again.	Gabe Black
	When no size is specified for an argument, push the decision about what size to use into the ISA by passing a size of -1.
2010-10-13	Mem: Change the CLREX flag to CLEAR_LL.	Gabe Black
	CLREX is the name of an ARM instruction, not a name for this generic flag.
2010-10-01	ARM: Make the TLB a little bit faster by moving most recently used items to ↵	Ali Saidi
	front of list
2010-10-01	ARM: Implement functional virtual to physical address translation	Ali Saidi
	for debugging and program introspection.
2010-10-01	Debug: Implement getArgument() and function skipping for ARM.	Ali Saidi
	In the process make add skipFuction() to handle isa specific function skipping instead of ifdefs and other ugliness. For almost all ABIs, 64 bit arguments can only start in even registers. Size is now passed to getArgument() so that 32 bit systems can make decisions about register selection for 64 bit arguments. The number argument is now passed by reference because getArgument() will need to change it based on the size of the argument and the current argument number. For ARM, if the argument number is odd and a 64-bit register is requested the number must first be incremented to because all 64 bit arguments are passed in an even argument register. Then the number will be incremented again to access both halves of the argument.
2010-10-01	ARM: Clean up use of TBit and JBit.	Ali Saidi
	Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code.
2010-09-14	CPU: Trim unnecessary includes from some common files.	Gabe Black
	This reduces the scope of those includes and makes it less likely for there to be a dependency loop. This also moves the hashing functions associated with ExtMachInst objects to be with the ExtMachInst definitions and out of utility.hh.
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
	Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-08-31	ARM: Get rid of the checkFpEnableFault function in ARM.	Gabe Black

2010-08-25	ARM: Support unaligned memory access.	Min Kyu Jeong
	Without this flag set, page-crossing requests were not split into two mem request. Depending on the alignment bit in the SCTLR, misaligned access could raise a fault. However it seems unnecessary to implement that.
2010-08-25	ARM: Seperate the queues of L1 and L2 walker states.	Gene WU

2010-08-25	ARM: Adding a bogus fault that does nothing.	Min Kyu Jeong
	This fault can used to flush the pipe, not including the faulting instruction. The particular case I needed this was for a self-modifying code. It needed to drain the store queue and force the following instruction to refetch from icache. DCCMVAC cp15 mcr instruction is modified to raise this fault.
2010-08-25	ARM: Remove ALPHA KSeg functions.	William Wang
	These were erronously copied years ago into the ARM directory.
2010-08-25	ARM: Limited implementation of dprintk.	Ali Saidi
	Does not work with vfp arguments or arguments passed on the stack.
2010-08-25	ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)	Min Kyu Jeong
	When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path
2010-08-25	ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing	Ali Saidi

2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
	Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict.
2010-08-25	ARM: Set the high bits in the part number so it's considered new by some code.	Ali Saidi

2010-08-25	ARM: Fix VFP enabled checks for mem instructions	Ali Saidi

2010-08-25	ARM: Seperate out the renamable bits in the FPSCR.	Gabe Black

2010-08-25	ARM: Eliminate some unused enums.	Gabe Black

2010-08-25	ARM: Fix type comparison warnings in Neon.	Gabe Black

2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP ↵	Gabe Black
	access is disabled.
2010-08-25	ARM: Implement all ARM SIMD instructions.	Gabe Black

2010-08-25	ARM: Expand the mode checking utility functions.	Gabe Black
	inUserMode now can take either a threadcontext or a CPSR value directly. If given a thread context it just extracts the CPSR and calls the other version. An inPrivelegedMode function was also implemented which just returns the opposite of inUserMode.
2010-08-23	ISA: Get rid of old, unused utility functions cluttering up the ISAs.	Gabe Black

2010-08-23	ARM: Improve printing of uop disassembly.	Min Kyu Jeong

2010-08-23	ARM: Clean up flattening for SPSR adding	Min Kyu Jeong

2010-08-23	ARM: Implement DBG instruction that doesn't do much for now.	Gene Wu

2010-08-23	MEM: Make CLREX a first class request operation and clear locks in caches ↵	Gene Wu
	when it in received
2010-08-23	ARM: Make sure that software prefetch instructions can't change the state of ↵	Gene Wu
	the TLB
2010-08-23	ARM: Don't write tracedata on writes, it might have been freed already.	Gene Wu

2010-08-23	ARM: Implement CLREX init/complete acc methods	Gene Wu

2010-08-23	ARM: Fix Uncachable TLB requests and decoding of xn bit	Gene Wu

2010-08-23	ARM: For non-cachable accesses set the UNCACHABLE flag	Gene Wu

2010-08-23	ARM: Implement DSB, DMB, ISB	Gene Wu

2010-08-23	ARM: Get SCTLR TE bit from reset SCTLR	Gene Wu

2010-08-23	ARM: Implement CLREX	Gene Wu

2010-08-23	ARM: BX instruction can be contitional if last instruction in a IT block	Gene Wu
	Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond.
2010-08-23	ARM: mark msr/mrs instructions as SerializeBefore/After	Min Kyu Jeong
	Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
	THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
2010-08-23	ARM: adding genMachineCheckFault() stub for ARM that doesn't panic	Min Kyu Jeong

2010-08-23	ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵	Gene Wu
	ARMv7
2010-08-23	ARM: Temporary local variables can't conflict with isa parser operands.	Gene Wu
	PC is an operand, so we can't have a temp called PC
2010-08-23	ARM: Exclusive accesses must be double word aligned	Ali Saidi

2010-08-23	ARM: Add some registers for big loads/stores to support neon.	Ali Saidi

2010-08-23	ARM: Decode neon memory instructions.	Ali Saidi

2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black