| Age | Commit message (Expand) | Author |
|---|
| 2019-05-18 | arm: Add an object file loader for linux and freebsd. | Gabe Black |
| 2019-05-17 | arch-arm: implement VMINNM and VMAXNM scalar version | Ciro Santilli |
| 2019-05-17 | arch-arm: implement VMINNM and VMAXNM SIMD version | Ciro Santilli |
| 2019-05-17 | arch-arm: rename operands to match spec in isa/formats/fp.isa | Ciro Santilli |
| 2019-05-14 | arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher | Javier Bueno |
| 2019-05-11 | arch-arm: Add initial support for SVE contiguous loads/stores | Giacomo Gabrielli |
| 2019-04-30 | arch: Stop using TheISA within the ISAs. | Gabe Black |
| 2019-04-29 | arch-arm: Faults DebugFlag now printing inst opcode if available | Giacomo Travaglini |
| 2019-04-29 | arch-arm: Report real instruction encoding when Undefined | Giacomo Travaglini |
| 2019-04-28 | arch, sim: Simplify the AuxVector type. | Gabe Black |
| 2019-04-28 | mem: Remove the ISA specialized versions of port proxy's read/write. | Gabe Black |
| 2019-04-28 | mem: Minimize the use of MemObject. | Gabe Black |
| 2019-04-26 | arch-arm: updateMiscReg not setting isHyp in aarch64 | Giacomo Travaglini |
| 2019-04-26 | arm: Factor some repetition out of the ProcessInfo constructor. | Gabe Black |
| 2019-04-25 | arm: Fix some style issues in stacktrace.cc. | Gabe Black |
| 2019-04-25 | arch-arm: Remove un-needed hyp flag in TLBI operations | Giacomo Travaglini |
| 2019-04-25 | arch-arm: Correct target EL field in TLBI operations | Giacomo Travaglini |
| 2019-04-11 | arch-arm: Enable PMSELR_EL0 read in PMU | Giacomo Travaglini |
| 2019-04-02 | dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt | Giacomo Travaglini |
| 2019-04-01 | dev-arm: Correct cast of template parameter | Andrea Mondelli |
| 2019-03-28 | arch-arm: Fix use of bitwise operators on booleans | Javier Setoain |
| 2019-03-28 | arch-arm: Fix index generation for VecElem operands | Giacomo Travaglini |
| 2019-03-25 | arch-arm: Add missing fall-through defaults | Javier Setoain |
| 2019-03-22 | sim-se: Fixed initialization array size | Tiago Muck |
| 2019-03-21 | dev-arm: ambiguous use of getPort() | Andrea Mondelli |
| 2019-03-19 | arch, cpu, dev, gpu, mem, sim, python: start using getPort. | Gabe Black |
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2019-03-11 | arch-arm: Fixing implicit fallthrough build errors | Ryan Gambord |
| 2019-03-01 | mem-cache: alias to mem::getMasterPort in TLB class | Andrea Mondelli |
| 2019-03-01 | arch-arm: implement floating point aarch32 VCVTA family | Ciro Santilli |
| 2019-02-18 | arch-arm: Move GICv3 detection at startup time | Giacomo Travaglini |
| 2019-02-13 | sim-se: update the arm kernel version | Ayaz Akram |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2019-02-08 | arch-arm: Fix Virtual interrupts in AArch64 | Giacomo Travaglini |
| 2019-02-08 | arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 | Giacomo Travaglini |
| 2019-02-08 | arch-arm: Allow ArmPPI usage for PMU | Giacomo Travaglini |
| 2019-02-08 | arch-arm: Fix initialization of PMU counters | Ruben Ayrapetyan |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-30 | arch-arm, configs: Create single instance of DTB autogeneration | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Remove floatReg operand type | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Use VecElem instead of FloatReg for FP instruction | Giacomo Travaglini |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Inital vector rename mode depending on A32/A64 | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Remove unused float operands | Giacomo Travaglini |
| 2019-01-23 | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 | Giacomo Travaglini |
| 2019-01-23 | arch-arm: IsStoreConditional flag set depending on flavor | Giacomo Travaglini |
| 2019-01-23 | arch-arm: Remove SWP and SWPB instructions | Giacomo Travaglini |
| 2019-01-23 | arm: Replace MiscReg with RegVal in utility.(hh|cc). | Gabe Black |
