| Age | Commit message (Expand) | Author |
|---|
| 2019-01-25 | arch-arm: Use VecElem instead of FloatReg for FP instruction | Giacomo Travaglini |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Inital vector rename mode depending on A32/A64 | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Remove unused float operands | Giacomo Travaglini |
| 2019-01-23 | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 | Giacomo Travaglini |
| 2019-01-23 | arch-arm: IsStoreConditional flag set depending on flavor | Giacomo Travaglini |
| 2019-01-23 | arch-arm: Remove SWP and SWPB instructions | Giacomo Travaglini |
| 2019-01-23 | arm: Replace MiscReg with RegVal in utility.(hh|cc). | Gabe Black |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-22 | arm: Get rid of some register type definitions. | Gabe Black |
| 2019-01-22 | arch-arm: implement the GDB XML target description for ARM | Ciro Santilli |
| 2019-01-22 | arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers | Giacomo Travaglini |
| 2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
| 2019-01-16 | arch: Make the ISA register types aliases for the global types. | Gabe Black |
| 2019-01-16 | arm: Make the fp register types 64 bits. | Gabe Black |
| 2019-01-16 | arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled | Giacomo Travaglini |
| 2019-01-16 | arch-arm: Added TLBI_ALL EL2 instruction | Anouk Van Laer |
| 2019-01-15 | arch-arm: Fix usage of RegId constructor for VecElem | Giacomo Travaglini |
| 2019-01-14 | arm: Stop using the FloatReg and FloatRegBits types. | Gabe Black |
| 2019-01-10 | sim-se, arch-arm: Add support for getdents64 | Javier Setoain |
| 2019-01-10 | arch-arm, sim-se: Add support for TLS in clone | Andreas Sandberg |
| 2019-01-10 | arch-arm, sim-se: Fix incorrect SP handling in clone | Andreas Sandberg |
| 2019-01-10 | sim-se: Refactor clone to avoid most ifdefs | Andreas Sandberg |
| 2019-01-10 | arch-arm, sim-se: Wire up syscalls needed for pthreads | Javier Setoain |
| 2019-01-10 | dev-arm: Add a GICv3 model | Jairo Balart |
| 2019-01-09 | arch-arm: Additional bits in misc ARM registers to use with the TLB and page ... | Ivan Pizarro |
| 2019-01-03 | arm: properly handle RES0/1 for SCTLRs | Curtis Dunham |
| 2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
| 2018-12-19 | arch-arm: Add Crypto in SE mode | Giacomo Travaglini |
| 2018-12-03 | arch-arm: correctly set floats from GDB on aarch64 | Ciro Santilli |
| 2018-12-03 | arch-arm: only change the pc address when GDB registers are set | Ciro Santilli |
| 2018-12-03 | arch-arm: fix the aarch64 GDB stub | Ciro Santilli |
| 2018-11-28 | arch-arm: Add missing template declaration | Nikos Nikoleris |
| 2018-11-28 | cpu,arch-arm: Initialise data members | Rekai Gonzalez-Alberquilla |
| 2018-11-28 | arch-arm: clang compilation fixes | Matteo Andreozzi |
| 2018-11-27 | arch, base, cpu, gpu, mem: Replace assert(0 or false with panic. | Gabe Black |
| 2018-11-14 | arch-arm: Print register name when warning on AT instructions | Giacomo Travaglini |
| 2018-11-07 | arch-arm: Deprecate usage of legacy bootloader patching | Giacomo Travaglini |
| 2018-11-07 | arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 | Giacomo Travaglini |
| 2018-11-07 | arch-arm: Implement AArch32 RVBAR | Giacomo Travaglini |
| 2018-11-07 | arch-arm: Remove SCTLR.VE bit | Giacomo Travaglini |
| 2018-11-07 | arch-arm: Refactor ISA::clear by adding a ISA::clear32 method | Giacomo Travaglini |
| 2018-11-07 | arch-arm: Remove MISCREG commented numbers | Giacomo Travaglini |
| 2018-11-05 | arch, arm: Return s1Req upon fault in s2Lookup | Anouk Van Laer |
| 2018-11-05 | arch, arm: Effect of AT instructions on descriptor handling | Anouk Van Laer |
| 2018-10-29 | syscall_emul: implement arm openat | Ciro Santilli |
| 2018-10-29 | arch-arm: FIXUP for the add PRFM PST instruction commit | Yuetsu Kodama |
| 2018-10-26 | arch-arm: We add PRFM PST instruction for arm | yuetsu.kodama |
| 2018-10-26 | arch-arm: IMPDEF for SYS instruction with CRn = {11, 15} | Giacomo Travaglini |
| 2018-10-26 | arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL | Giacomo Travaglini |
